在 2024/3/7 11:02, Jie Hai 写道:
This patch adds names for all registers to be dumped.
For those who can be directly accessed by their addresses,
a new structure containing both name and address is added
and the related arrays is refactored and renamed.
For the remaining modules, there may be different meanings
on different platforms for the same field. Therefore, two
name fields are provided.
There are some 64-bit registers, dump them as two 32-bit
registers.
Signed-off-by: Jie Hai <haij...@huawei.com>
---
drivers/net/hns3/hns3_regs.c | 877 ++++++++++++++++++++++++++++++++---
1 file changed, 801 insertions(+), 76 deletions(-)
diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c
index b1c0d538a3c8..b7e4f78eecde 100644
--- a/drivers/net/hns3/hns3_regs.c
+++ b/drivers/net/hns3/hns3_regs.c
@@ -14,67 +14,84 @@
<...>
+struct direct_reg_list {
+ const char *name;
+ uint32_t addr;
+};
+
+#define STR(s) #s
please use RTE_STR()
+
+static const struct direct_reg_list cmdq_reg_list[] = {
+ {STR(HNS3_CMDQ_TX_ADDR_L_REG), HNS3_CMDQ_TX_ADDR_L_REG},
+ {STR(HNS3_CMDQ_TX_ADDR_H_REG), HNS3_CMDQ_TX_ADDR_H_REG},
+ {STR(HNS3_CMDQ_TX_DEPTH_REG), HNS3_CMDQ_TX_DEPTH_REG},
+ {STR(HNS3_CMDQ_TX_TAIL_REG), HNS3_CMDQ_TX_TAIL_REG},
+ {STR(HNS3_CMDQ_TX_HEAD_REG), HNS3_CMDQ_TX_HEAD_REG},
+ {STR(HNS3_CMDQ_RX_ADDR_L_REG), HNS3_CMDQ_RX_ADDR_L_REG},
+ {STR(HNS3_CMDQ_RX_ADDR_H_REG), HNS3_CMDQ_RX_ADDR_H_REG},
+ {STR(HNS3_CMDQ_RX_DEPTH_REG), HNS3_CMDQ_RX_DEPTH_REG},
+ {STR(HNS3_CMDQ_RX_TAIL_REG), HNS3_CMDQ_RX_TAIL_REG},
+ {STR(HNS3_CMDQ_RX_HEAD_REG), HNS3_CMDQ_RX_HEAD_REG},
+ {STR(HNS3_VECTOR0_CMDQ_SRC_REG), HNS3_VECTOR0_CMDQ_SRC_REG},
+ {STR(HNS3_CMDQ_INTR_STS_REG), HNS3_CMDQ_INTR_STS_REG},
+ {STR(HNS3_CMDQ_INTR_EN_REG), HNS3_CMDQ_INTR_EN_REG},
+ {STR(HNS3_CMDQ_INTR_GEN_REG), HNS3_CMDQ_INTR_GEN_REG},
+};
+
+static const struct direct_reg_list common_reg_list[] = {
+ {STR(HNS3_MISC_VECTOR_REG_BASE), HNS3_MISC_VECTOR_REG_BASE},
+ {STR(HNS3_VECTOR0_OTER_EN_REG), HNS3_VECTOR0_OTER_EN_REG},
+ {STR(HNS3_MISC_RESET_STS_REG), HNS3_MISC_RESET_STS_REG},
+ {STR(HNS3_VECTOR0_OTHER_INT_STS_REG), HNS3_VECTOR0_OTHER_INT_STS_REG},
+ {STR(HNS3_GLOBAL_RESET_REG), HNS3_GLOBAL_RESET_REG},
+ {STR(HNS3_FUN_RST_ING), HNS3_FUN_RST_ING},
+ {STR(HNS3_GRO_EN_REG), HNS3_GRO_EN_REG},
+};
+
+static const struct direct_reg_list common_vf_reg_list[] = {
+ {STR(HNS3_MISC_VECTOR_REG_BASE), HNS3_MISC_VECTOR_REG_BASE},
+ {STR(HNS3_FUN_RST_ING), HNS3_FUN_RST_ING},
+ {STR(HNS3_GRO_EN_REG), HNS3_GRO_EN_REG},
+};
+
+static const struct direct_reg_list ring_reg_list[] = {
+ {STR(HNS3_RING_RX_BASEADDR_L_REG), HNS3_RING_RX_BASEADDR_L_REG},
+ {STR(HNS3_RING_RX_BASEADDR_H_REG), HNS3_RING_RX_BASEADDR_H_REG},
+ {STR(HNS3_RING_RX_BD_NUM_REG), HNS3_RING_RX_BD_NUM_REG},
+ {STR(HNS3_RING_RX_BD_LEN_REG), HNS3_RING_RX_BD_LEN_REG},
+ {STR(HNS3_RING_RX_EN_REG), HNS3_RING_RX_EN_REG},
+ {STR(HNS3_RING_RX_MERGE_EN_REG), HNS3_RING_RX_MERGE_EN_REG},
+ {STR(HNS3_RING_RX_TAIL_REG), HNS3_RING_RX_TAIL_REG},
+ {STR(HNS3_RING_RX_HEAD_REG), HNS3_RING_RX_HEAD_REG},
+ {STR(HNS3_RING_RX_FBDNUM_REG), HNS3_RING_RX_FBDNUM_REG},
+ {STR(HNS3_RING_RX_OFFSET_REG), HNS3_RING_RX_OFFSET_REG},
+ {STR(HNS3_RING_RX_FBD_OFFSET_REG), HNS3_RING_RX_FBD_OFFSET_REG},
+ {STR(HNS3_RING_RX_STASH_REG), HNS3_RING_RX_STASH_REG},
+ {STR(HNS3_RING_RX_BD_ERR_REG), HNS3_RING_RX_BD_ERR_REG},
+ {STR(HNS3_RING_TX_BASEADDR_L_REG), HNS3_RING_TX_BASEADDR_L_REG},
+ {STR(HNS3_RING_TX_BASEADDR_H_REG), HNS3_RING_TX_BASEADDR_H_REG},
+ {STR(HNS3_RING_TX_BD_NUM_REG), HNS3_RING_TX_BD_NUM_REG},
+ {STR(HNS3_RING_TX_EN_REG), HNS3_RING_TX_EN_REG},
+ {STR(HNS3_RING_TX_PRIORITY_REG), HNS3_RING_TX_PRIORITY_REG},
+ {STR(HNS3_RING_TX_TC_REG), HNS3_RING_TX_TC_REG},
+ {STR(HNS3_RING_TX_MERGE_EN_REG), HNS3_RING_TX_MERGE_EN_REG},
+ {STR(HNS3_RING_TX_TAIL_REG), HNS3_RING_TX_TAIL_REG},
+ {STR(HNS3_RING_TX_HEAD_REG), HNS3_RING_TX_HEAD_REG},
+ {STR(HNS3_RING_TX_FBDNUM_REG), HNS3_RING_TX_FBDNUM_REG},
+ {STR(HNS3_RING_TX_OFFSET_REG), HNS3_RING_TX_OFFSET_REG},
+ {STR(HNS3_RING_TX_EBD_NUM_REG), HNS3_RING_TX_EBD_NUM_REG},
+ {STR(HNS3_RING_TX_EBD_OFFSET_REG), HNS3_RING_TX_EBD_OFFSET_REG},
+ {STR(HNS3_RING_TX_BD_ERR_REG), HNS3_RING_TX_BD_ERR_REG},
+ {STR(HNS3_RING_EN_REG), HNS3_RING_EN_REG},
+};
+
+static const struct direct_reg_list tqp_intr_reg_list[] = {
+ {STR(HNS3_TQP_INTR_CTRL_REG), HNS3_TQP_INTR_CTRL_REG},
+ {STR(HNS3_TQP_INTR_GL0_REG), HNS3_TQP_INTR_GL0_REG},
+ {STR(HNS3_TQP_INTR_GL1_REG), HNS3_TQP_INTR_GL1_REG},
+ {STR(HNS3_TQP_INTR_GL2_REG), HNS3_TQP_INTR_GL2_REG},
+ {STR(HNS3_TQP_INTR_RL_REG), HNS3_TQP_INTR_RL_REG},
+};
static const uint32_t hns3_dfx_reg_opcode_list[] = {
HNS3_OPC_DFX_BIOS_COMMON_REG,
@@ -91,6 +108,708 @@ static const uint32_t hns3_dfx_reg_opcode_list[] = {
HNS3_OPC_DFX_SSU_REG_2
};
+struct hns3_reg_entry {
+ const char *new_name;
+ const char *old_name;
+};
This is not good.
+
+static struct hns3_reg_entry regs_32_bit_list[] = {
+ {"ssu_common_err_int"},
+ {"ssu_port_based_err_int"},
+ {"ssu_fifo_overflow_int"},
+ {"ssu_ets_tcg_int"},
+ {"ssu_bp_status_0"},
+ {"ssu_bp_status_1"},
+
+ {"ssu_bp_status_2"},
+ {"ssu_bp_status_3"},
+ {"ssu_bp_status_4"},
+ {"ssu_bp_status_5"},
+ {"ssu_mac_tx_pfc_ind"},
+ {"ssu_mac_rx_pfc_ind"},
+
+ {"ssu_rx_oq_drop_pkt_cnt"},
+ {"ssu_tx_oq_drop_pkt_cnt"},
<...>
+
+static struct hns3_reg_entry dfx_rtc_reg_list[] = {
+ {"rtc_rsv0"},
+ {"lge_igu_afifo_dfx_0"},
+ {"lge_igu_afifo_dfx_1"},
+ {"lge_igu_afifo_dfx_2"},
+ {"lge_igu_afifo_dfx_3"},
+ {"lge_igu_afifo_dfx_4"},
+
+ {"lge_igu_afifo_dfx_5"},
+ {"lge_igu_afifo_dfx_6"},
+ {"lge_igu_afifo_dfx_7"},
+ {"lge_egu_afifo_dfx_0"},
+ {"lge_egu_afifo_dfx_1"},
+ {"lge_egu_afifo_dfx_2"},
+
+ {"lge_egu_afifo_dfx_3"},
+ {"lge_egu_afifo_dfx_4"},
+ {"lge_egu_afifo_dfx_5"},
+ {"lge_egu_afifo_dfx_6"},
+ {"lge_egu_afifo_dfx_7"},
+ {"cge_igu_afifo_dfx_0"},
+
+ {"cge_igu_afifo_dfx_1"},
+ {"cge_egu_afifo_dfx_0"},
+ {"cge_egu_afifo_dfx_i"},
+ {"rtc_rsv1"},
+ {"rtc_rsv2"},
+ {"rtc_rsv3"},
+};
+
+static struct hns3_reg_entry dfx_ppp_reg_list[] = {
+ {"ppp_rsv0"},
+ {"ppp_drop_from_prt_pkt_cnt"},
+ {"ppp_drop_from_host_pkt_cnt"},
+ {"ppp_drop_tx_vlan_proc_cnt"},
+ {"ppp_drop_mng_cnt"},
+ {"ppp_drop_fd_cnt"},
+
+ {"ppp_drop_no_dst_cnt"},
+ {"ppp_drop_mc_mbid_full_cnt"},
+ {"ppp_drop_sc_filtered"},
+ {"ppp_ppp_mc_drop_pkt_cnt"},
+ {"ppp_drop_pt_cnt"},
+ {"ppp_drop_mac_anti_spoof_cnt"},
+
+ {"ppp_drop_ig_vfv_cnt"},
+ {"ppp_drop_ig_prtv_cnt"},
+ {"ppp_drop_cnm_pfc_pause_cnt"},
+ {"ppp_drop_torus_tc_cnt"},
+ {"ppp_drop_torus_lpbk_cnt"},
+ {"ppp_ppp_hfs_sts"},
+
+ {"ppp_mc_rslt_sts"},
+ {"ppp_p3u_sts"},
+ {"ppp_rsv1", "ppp_rslt_descr_sts"},
+ {"ppp_umv_sts_0"},
+ {"ppp_umv_sts_1"},
+ {"ppp_vfv_sts"},
+
+ {"ppp_gro_key_cnt"},
+ {"ppp_gro_info_cnt"},
+ {"ppp_gro_drop_cnt"},
+ {"ppp_gro_out_cnt"},
+ {"ppp_gro_key_match_data_cnt"},
+ {"ppp_gro_key_match_tcam_cnt"},
+
+ {"ppp_gro_info_match_cnt"},
+ {"ppp_gro_free_entry_cnt"},
+ {"ppp_gro_inner_dfx_signal"},
+ {"ppp_rsv2"},
+ {"ppp_rsv3"},
+ {"ppp_rsv4"},
+
+ {"ppp_get_rx_pkt_cnt_l"},
+ {"ppp_get_rx_pkt_cnt_h"},
+ {"ppp_get_tx_pkt_cnt_l"},
+ {"ppp_get_tx_pkt_cnt_h"},
+ {"ppp_send_uc_prt2host_pkt_cnt_l"},
+ {"ppp_send_uc_prt2host_pkt_cnt_h"},
+
+ {"ppp_send_uc_prt2prt_pkt_cnt_l"},
+ {"ppp_send_uc_prt2prt_pkt_cnt_h"},
+ {"ppp_send_uc_host2host_pkt_cnt_l"},
+ {"ppp_send_uc_host2host_pkt_cnt_h"},
+ {"ppp_send_uc_host2prt_pkt_cnt_l"},
+ {"ppp_send_uc_host2prt_pkt_cnt_h"},
+
+ {"ppp_send_mc_from_prt_cnt_l"},
+ {"ppp_send_mc_from_prt_cnt_h"},
+ {"ppp_send_mc_from_host_cnt_l"},
+ {"ppp_send_mc_from_host_cnt_h"},
+ {"ppp_ssu_mc_rd_cnt_l"},
+ {"ppp_ssu_mc_rd_cnt_h"},
+
+ {"ppp_ssu_mc_drop_cnt_l"},
+ {"ppp_ssu_mc_drop_cnt_h"},
+ {"ppp_ssu_mc_rd_pkt_cnt_l"},
+ {"ppp_ssu_mc_rd_pkt_cnt_h"},
+ {"ppp_mc_2host_pkt_cnt_l"},
+ {"ppp_mc_2host_pkt_cnt_h"},
+
+ {"ppp_mc_2prt_pkt_cnt_l"},
+ {"ppp_mc_2prt_pkt_cnt_h"},
+ {"ppp_ntsnos_pkt_cnt_l"},
+ {"ppp_ntsnos_pkt_cnt_h"},
+ {"ppp_ntup_pkt_cnt_l"},
+ {"ppp_ntup_pkt_cnt_h"},
+
+ {"ppp_ntlcl_pkt_cnt_l"},
+ {"ppp_ntlcl_pkt_cnt_h"},
+ {"ppp_nttgt_pkt_cnt_l"},
+ {"ppp_nttgt_pkt_cnt_h"},
+ {"ppp_rtns_pkt_cnt_l"},
+ {"ppp_rtns_pkt_cnt_h"},
+
+ {"ppp_rtlpbk_pkt_cnt_l"},
+ {"ppp_rtlpbk_pkt_cnt_h"},
+ {"ppp_nr_pkt_cnt_l"},
+ {"ppp_nr_pkt_cnt_h"},
+ {"ppp_rr_pkt_cnt_l"},
+ {"ppp_rr_pkt_cnt_h"},
+
+ {"ppp_mng_tbl_hit_cnt_l"},
+ {"ppp_mng_tbl_hit_cnt_h"},
+ {"ppp_fd_tbl_hit_cnt_l"},
+ {"ppp_fd_tbl_hit_cnt_h"},
+ {"ppp_fd_lkup_cnt_l"},
+ {"ppp_fd_lkup_cnt_h"},
+
+ {"ppp_bc_hit_cnt"},
+ {"ppp_bc_hit_cnt_h"},
+ {"ppp_um_tbl_uc_hit_cnt"},
+ {"ppp_um_tbl_uc_hit_cnt_h"},
+ {"ppp_um_tbl_mc_hit_cnt"},
+ {"ppp_um_tbl_mc_hit_cnt_h"},
+
+ {"ppp_um_tbl_snq_hit_cnt_l", "ppp_um_tbl_vmdq1_hit_cnt_l"},
+ {"ppp_um_tbl_snq_hit_cnt_h", "ppp_um_tbl_vmdq1_hit_cnt_h"},
+ {"ppp_rsv5", "ppp_mta_tbl_hit_cnt_l"},
+ {"ppp_rsv6", "ppp_mta_tbl_hit_cnt_h"},
If there are different names for these register,
how about use a common name like ppp_func_reg1、ppp_func_reg2?
or do not show the new register name on latter platform and only use the
original name, "ppp_rsv5/6".
Because we don't know if this register name will be changed on the new
plaform in furture.
+ {"ppp_fwd_bonding_hit_cnt_l"},
+ {"ppp_fwd_bonding_hit_cnt_h"},
+
+ {"ppp_promisc_tbl_hit_cnt_l"},
+ {"ppp_promisc_tbl_hit_cnt_h"},
+ {"ppp_get_tunl_pkt_cnt_l"},
+ {"ppp_get_tunl_pkt_cnt_h"},
+ {"ppp_get_bmc_pkt_cnt_l"},
+ {"ppp_get_bmc_pkt_cnt_h"},
+
+ {"ppp_send_uc_prt2bmc_pkt_cnt_l"},
+ {"ppp_send_uc_prt2bmc_pkt_cnt_h"},
+ {"ppp_send_uc_host2bmc_pkt_cnt_l"},
+ {"ppp_send_uc_host2bmc_pkt_cnt_h"},
+ {"ppp_send_uc_bmc2host_pkt_cnt_l"},
+ {"ppp_send_uc_bmc2host_pkt_cnt_h"},
+
+ {"ppp_send_uc_bmc2prt_pkt_cnt_l"},
+ {"ppp_send_uc_bmc2prt_pkt_cnt_h"},
+ {"ppp_mc_2bmc_pkt_cnt_l"},
+ {"ppp_mc_2bmc_pkt_cnt_h"},
+ {"ppp_rsv7", "ppp_vlan_mirr_cnt_l"},
+ {"ppp_rsv8", "ppp_vlan_mirr_cnt_h"},
+
+ {"ppp_rsv9", "ppp_ig_mirr_cnt_l"},
+ {"ppp_rsv10", "ppp_ig_mirr_cnt_h"},
+ {"ppp_rsv11", "ppp_eg_mirr_cnt_l"},
+ {"ppp_rsv12", "ppp_eg_mirr_cnt_h"},
+ {"ppp_rx_default_host_hit_cnt_l"},
+ {"ppp_rx_default_host_hit_cnt_h"},
+
+ {"ppp_lan_pair_cnt_l"},
+ {"ppp_lan_pair_cnt_h"},
+ {"ppp_um_tbl_mc_hit_pkt_cnt_l"},
+ {"ppp_um_tbl_mc_hit_pkt_cnt_h"},
+ {"ppp_mta_tbl_hit_pkt_cnt_l"},
+ {"ppp_mta_tbl_hit_pkt_cnt_h"},
+
+ {"ppp_promisc_tbl_hit_pkt_cnt_l"},
+ {"ppp_promisc_tbl_hit_pkt_cnt_h"},
+ {"ppp_rsv13"},
+ {"ppp_rsv14"},
+ {"ppp_rsv15"},
+ {"ppp_rsv16"},
+};
+
<...>
