>+uint32_t *credit_pool[DLB2_NUM_QUEUE_TYPES]; /* use __atomic builtins */
Spell check complains here you can add a space after the '*' if you don’t want that complaint. (e.g. uint32_t * credit_pool). > case nb_events_limit: > return dlb2->new_event_limit; > case inflight_events: > - return __atomic_load_n(&dlb2->inflights, __ATOMIC_SEQ_CST); > + return rte_atomic_load_explicit(&dlb2->inflights, > +rte_memory_order_seq_cst); >+This is more a question to the driver maintainer, but why does this load need >to be CST? What stores need it to be ordered against. Even load-acquire seems >overkill to me, but I may well be missing something. I am not sure of this why previous maintainers went this way and I am looking into it . To me now it looks like the strict requirements can be changed. If so I will submit a patch later to change and address this.
