When application configures a DIR port with CQ depth less than 8, DLB PMD
sets port's cq_depth as 8 and token reservation is used to make the
effective cq_depth smaller. However, while setting port's cq_depth_mask
application configured CQ depth was used resulting in reading incorrect
cachelines while dequeuing. Use PMD calculated CQ depth for cq_depth_mask
calculation.
Signed-off-by: Pravin Pathak <pravin.pat...@intel.com>
Signed-off-by: Tirthendu Sarkar <tirthendu.sar...@intel.com>
---
drivers/event/dlb2/dlb2.c | 4 ++--
drivers/event/dlb2/pf/dlb2_pf.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c
index 286241ea41..a0e673b96b 100644
--- a/drivers/event/dlb2/dlb2.c
+++ b/drivers/event/dlb2/dlb2.c
@@ -1951,9 +1951,9 @@ dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,
qm_port->cq_idx_unmasked = 0;
if (dlb2->poll_mode == DLB2_CQ_POLL_MODE_SPARSE)
- qm_port->cq_depth_mask = (cfg.cq_depth * 4) - 1;
+ qm_port->cq_depth_mask = (qm_port->cq_depth * 4) - 1;
else
- qm_port->cq_depth_mask = cfg.cq_depth - 1;
+ qm_port->cq_depth_mask = qm_port->cq_depth - 1;
qm_port->gen_bit_shift = rte_popcount32(qm_port->cq_depth_mask);
/* starting value of gen bit - it toggles at wrap time */
diff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c
index ed4e6e424c..31b5487d85 100644
--- a/drivers/event/dlb2/pf/dlb2_pf.c
+++ b/drivers/event/dlb2/pf/dlb2_pf.c
@@ -400,7 +400,7 @@ dlb2_pf_dir_port_create(struct dlb2_hw_dev *handle,
/* Calculate the port memory required, and round up to the nearest
* cache line.
*/
- alloc_sz = cfg->cq_depth * qe_sz;
+ alloc_sz = RTE_MAX(cfg->cq_depth, DLB2_MIN_HARDWARE_CQ_DEPTH) * qe_sz;
alloc_sz = RTE_CACHE_LINE_ROUNDUP(alloc_sz);
port_base = dlb2_alloc_coherent_aligned(&mz, &cq_base, alloc_sz,
--
2.25.1
