[PATCH] net/gve: properly disable interrupts on DQ

[Joshua Washington]

When starting RX and TX queues in the DQ queue format, the driver was
erroneously writing GVE_IRQ_MASK to the IRQ doorbell. GQ and DQ have
different interrupt register layouts, so writing this bit is incorrect.
Update the register write to properly enable NO_INT_MODE for DQO.

Fixes: b044845bb015 ("net/gve: support queue start/stop")
Cc: sta...@dpdk.org

Signed-off-by: Joshua Washington <joshw...@google.com>
Reviewed-by: Praveen Kaligineedi <pkaligine...@google.com>
---
 drivers/net/gve/base/gve_desc_dqo.h | 4 ++++
 drivers/net/gve/gve_rx_dqo.c        | 4 +++-
 drivers/net/gve/gve_tx_dqo.c        | 4 +++-
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/net/gve/base/gve_desc_dqo.h 
b/drivers/net/gve/base/gve_desc_dqo.h
index bb4a18d4d1..71d9d60bb9 100644
--- a/drivers/net/gve/base/gve_desc_dqo.h
+++ b/drivers/net/gve/base/gve_desc_dqo.h
@@ -248,4 +248,8 @@ GVE_CHECK_STRUCT_LEN(32, gve_rx_compl_desc_dqo);
  */
 #define GVE_RX_BUF_THRESH_DQO 32
 
+/* GVE IRQ */
+#define GVE_NO_INT_MODE_DQO BIT(30)
+#define GVE_ITR_NO_UPDATE_DQO (3 << 3)
+
 #endif /* _GVE_DESC_DQO_H_ */
diff --git a/drivers/net/gve/gve_rx_dqo.c b/drivers/net/gve/gve_rx_dqo.c
index 285c6ddd61..0103add985 100644
--- a/drivers/net/gve/gve_rx_dqo.c
+++ b/drivers/net/gve/gve_rx_dqo.c
@@ -415,7 +415,9 @@ gve_rx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t 
rx_queue_id)
 
        rxq->qrx_tail = &hw->db_bar2[rte_be_to_cpu_32(rxq->qres->db_index)];
 
-       rte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), rxq->ntfy_addr);
+       rte_write32(rte_cpu_to_le_32(GVE_NO_INT_MODE_DQO |
+                                    GVE_ITR_NO_UPDATE_DQO),
+                   rxq->ntfy_addr);
 
        ret = gve_rxq_mbufs_alloc_dqo(rxq);
        if (ret != 0) {
diff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c
index 6984f92443..0a16b6a52d 100644
--- a/drivers/net/gve/gve_tx_dqo.c
+++ b/drivers/net/gve/gve_tx_dqo.c
@@ -415,7 +415,9 @@ gve_tx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t 
tx_queue_id)
        txq->qtx_head =
                &hw->cnt_array[rte_be_to_cpu_32(txq->qres->counter_index)];
 
-       rte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), txq->ntfy_addr);
+       rte_write32(rte_cpu_to_le_32(GVE_NO_INT_MODE_DQO |
+                                    GVE_ITR_NO_UPDATE_DQO),
+                   txq->ntfy_addr);
 
        dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 
-- 
2.50.1.565.gc32cd1483b-goog