Introduce helper functions to perform external PHY register read and write operations. These helpers currently support only IEEE Clause 22 PHY access, providing a simple and consistent API for accessing standard 16‑bit MII registers on external PHY devices.
This patch does not implement Clause 45 transactions; support for C45 access can be added in future updates as needed. No functional changes are introduced for existing drivers. The new helpers will be used by subsequent patches that require external PHY management. Signed-off-by: Ashok Kumar Natarajan <[email protected]> --- .mailmap | 1 + drivers/net/axgbe/axgbe_ethdev.h | 3 +++ drivers/net/axgbe/axgbe_phy_impl.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/.mailmap b/.mailmap index 8bbfcc1703..6f951bcd92 100644 --- a/.mailmap +++ b/.mailmap @@ -165,6 +165,7 @@ Ashish Paul <[email protected]> Ashish Sadanandan <[email protected]> Ashish Shah <[email protected]> Ashok Kaladi <[email protected]> +Ashok Kumar Natarajan <[email protected]> Ashwin Sekhar T K <[email protected]> <[email protected]> Asim Jamshed <[email protected]> Atul Patel <[email protected]> diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h index b94a7f3562..12d77cd520 100644 --- a/drivers/net/axgbe/axgbe_ethdev.h +++ b/drivers/net/axgbe/axgbe_ethdev.h @@ -398,6 +398,9 @@ struct axgbe_phy_impl_if { /* Pre/Post KR training enablement support */ void (*kr_training_pre)(struct axgbe_port *); void (*kr_training_post)(struct axgbe_port *); + + int (*read)(struct axgbe_port *port, int addr, int reg); + int (*write)(struct axgbe_port *port, int addr, int reg, u16 val); }; struct axgbe_phy_if { diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c index 9249e11335..4f3cc63836 100644 --- a/drivers/net/axgbe/axgbe_phy_impl.c +++ b/drivers/net/axgbe/axgbe_phy_impl.c @@ -251,6 +251,8 @@ static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata, enum axgbe_mb_cmd cmd, enum axgbe_mb_subcmd sub_cmd); static void axgbe_phy_rrc(struct axgbe_port *pdata); +static int axgbe_phy_get_comm_ownership(struct axgbe_port *pdata); +static void axgbe_phy_put_comm_ownership(struct axgbe_port *pdata); static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata, struct axgbe_i2c_op *i2c_op) @@ -258,6 +260,30 @@ static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata, return pdata->i2c_if.i2c_xfer(pdata, i2c_op); } +static int axgbe_phy_mii_read_c22(struct axgbe_port *pdata, int addr, int reg) +{ + int ret, regval; + ret = axgbe_phy_get_comm_ownership(pdata); + if (ret) + return -1; + regval = pdata->hw_if.read_ext_mii_regs_c22(pdata, addr, reg); + axgbe_phy_put_comm_ownership(pdata); + return regval; +} + +static int axgbe_phy_mii_write_c22(struct axgbe_port *pdata, int addr, + int reg, u16 val) +{ + int ret, regval; + ret = axgbe_phy_get_comm_ownership(pdata); + if (ret) + return -1; + regval = pdata->hw_if.write_ext_mii_regs_c22(pdata, addr, reg, val); + axgbe_phy_put_comm_ownership(pdata); + return regval; +} + + static int axgbe_phy_redrv_write(struct axgbe_port *pdata, unsigned int reg, unsigned int val) { @@ -2542,4 +2568,7 @@ void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if) phy_impl->kr_training_pre = axgbe_phy_kr_training_pre; phy_impl->kr_training_post = axgbe_phy_kr_training_post; + + phy_impl->read = axgbe_phy_mii_read_c22; + phy_impl->write = axgbe_phy_mii_write_c22; } -- 2.34.1
