Provide devarg option to configure RXC time granularity for reassembly handling.
It will be set as rxc_step=<val> for nix device. e.g.: 0002:02:00.0,rxc_step=10000 Signed-off-by: Rahul Bhansali <[email protected]> --- doc/guides/nics/cnxk.rst | 14 ++++++++++++++ drivers/net/cnxk/cn20k_ethdev.c | 1 + drivers/net/cnxk/cnxk_ethdev_devargs.c | 26 +++++++++++++++++++++++++- 3 files changed, 40 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst index 9e758a1b5e..c43c70b275 100644 --- a/doc/guides/nics/cnxk.rst +++ b/doc/guides/nics/cnxk.rst @@ -494,6 +494,20 @@ Runtime Config Options -a 0002:02:00.0,disable_xqe_drop=1 +- ``Configure RXC time step`` (default ``1000``) + + RXC time step/granularity for reassembly can be specified by + ``rxc_step`` ``devargs`` parameter. + + For example:: + + -a 0002:02:00.0,rxc_step=10000 + + With the above configuration, reassembly time step will be set to 10000 + microseconds. Default RXC time step will be set to 1000 microseconds + when reassembly is configured. + It will be used for OCTEON CN20K SoC family. + .. note:: Above devarg parameters are configurable per device, user needs to pass the diff --git a/drivers/net/cnxk/cn20k_ethdev.c b/drivers/net/cnxk/cn20k_ethdev.c index 4a3d163c75..f08079f612 100644 --- a/drivers/net/cnxk/cn20k_ethdev.c +++ b/drivers/net/cnxk/cn20k_ethdev.c @@ -705,6 +705,7 @@ cn20k_nix_reassembly_conf_set(struct rte_eth_dev *eth_dev, } } + rxc_time_cfg.step = dev->nix.rxc_step; rc = roc_nix_reassembly_configure(&rxc_time_cfg, conf->timeout_ms); if (rc) { plt_err("Nix reassembly_configure failed rc=%d", rc); diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c index 68e6b1d190..da8fc83f9d 100644 --- a/drivers/net/cnxk/cnxk_ethdev_devargs.c +++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c @@ -64,6 +64,25 @@ parse_ipsec_in_spi_range(const char *key, const char *value, void *extra_args) return 0; } +static int +parse_rxc_step(const char *key, const char *value, void *extra_args) +{ + RTE_SET_USED(key); + uint32_t val; + + errno = 0; + val = strtoul(value, NULL, 0); + if (errno) + return -EINVAL; + + if (val > ROC_NIX_INL_REAS_STEP_MAX) + return -EINVAL; + + *(uint32_t *)extra_args = val; + + return 0; +} + static int parse_ipsec_out_max_sa(const char *key, const char *value, void *extra_args) { @@ -283,6 +302,7 @@ parse_val_u16(const char *key, const char *value, void *extra_args) #define CNXK_CUSTOM_INB_SA "custom_inb_sa" #define CNXK_FORCE_TAIL_DROP "force_tail_drop" #define CNXK_DIS_XQE_DROP "disable_xqe_drop" +#define CNXK_RXC_STEP "rxc_step" int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) @@ -314,6 +334,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) uint16_t lock_rx_ctx = 0; uint16_t rx_inj_ena = 0; uint16_t no_inl_dev = 0; + uint32_t rxc_step = 0; memset(&sdp_chan, 0, sizeof(sdp_chan)); memset(&pre_l2_info, 0, sizeof(struct flow_pre_l2_size_info)); @@ -370,6 +391,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) rte_kvargs_process(kvlist, CNXK_CUSTOM_INB_SA, &parse_flag, &custom_inb_sa); rte_kvargs_process(kvlist, CNXK_FORCE_TAIL_DROP, &parse_flag, &force_tail_drop); rte_kvargs_process(kvlist, CNXK_DIS_XQE_DROP, &parse_flag, &dis_xqe_drop); + rte_kvargs_process(kvlist, CNXK_RXC_STEP, &parse_rxc_step, &rxc_step); rte_kvargs_free(kvlist); null_devargs: @@ -413,6 +435,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) dev->nix.rx_inj_ena = rx_inj_ena; dev->nix.force_tail_drop = force_tail_drop; dev->nix.dis_xqe_drop = !!dis_xqe_drop; + dev->nix.rxc_step = rxc_step; return 0; exit: return -EINVAL; @@ -439,4 +462,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_cnxk, CNXK_NIX_RX_INJ_ENABLE "=1" CNXK_CUSTOM_META_AURA_DIS "=1" CNXK_FORCE_TAIL_DROP "=1" - CNXK_DIS_XQE_DROP "=1"); + CNXK_DIS_XQE_DROP "=1" + CNXK_RXC_STEP "=<0-1048575>"); -- 2.34.1
