From: Grzegorz Nitka <[email protected]>
Fix incorrect 'adjust the timer' programming sequence for E830 devices
series. Only shadow registers GLTSYN_SHADJ were programmed in the current
implementation. According to the specification [1], write to command
GLTSYN_CMD register is also required with CMD field set to "Adjust the
Time" value, for the timer adjustment to take the effect.
The flow was broken for the adjustment less than S32_MAX/MIN range
(around +/- 2 seconds). For bigger adjustment, non-atomic programming
flow is used, involving set timer programming. Non-atomic flow is
implemented correctly.
Fixes: 881169950d80 ("net/ice/base: implement initial PTP support for E830")
Cc: [email protected]
Signed-off-by: Soumyadeep Hore <[email protected]>
Signed-off-by: Grzegorz Nitka <[email protected]>
---
drivers/net/intel/ice/base/ice_ptp_hw.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/intel/ice/base/ice_ptp_hw.c
b/drivers/net/intel/ice/base/ice_ptp_hw.c
index 7d16965674..5688f969ce 100644
--- a/drivers/net/intel/ice/base/ice_ptp_hw.c
+++ b/drivers/net/intel/ice/base/ice_ptp_hw.c
@@ -6083,7 +6083,7 @@ int ice_ptp_write_incval_locked(struct ice_hw *hw, u64
incval,
*/
int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq)
{
- int err;
+ int err = 0;
u8 tmr_idx;
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
@@ -6101,8 +6101,8 @@ int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool
lock_sbq)
err = ice_ptp_prep_phy_adj_eth56g(hw, adj, lock_sbq);
break;
case ICE_PHY_E830:
- /* E830 sync PHYs automatically after setting GLTSYN_SHADJ */
- return 0;
+ /* E830 sync PHYs automatically after setting cmd register */
+ break;
case ICE_PHY_E810:
err = ice_ptp_prep_phy_adj_e810(hw, adj, lock_sbq);
break;
--
2.47.1
