> #ifdef RTE_ARCH_64
> /* lwu is RV64-only: zero-extends to avoid sign-bit pollution */
> asm volatile("lwu %0, 0(%1)" : "=r"(val) : "r"(addr) : "memory");
> #else
> /* on RV32, lw is full-width, no extension needed */
> asm volatile("lw %0, 0(%1)" : "=r"(val) : "r"(addr) : "memory");
> #endif
DPDK RISC-V does not support 32-bit. config/riscv/meson.build:
if not dpdk_conf.get('RTE_ARCH_64')
error('Only 64-bit compiles are supported for this platform type')
We can remove all the #ifdef RTE_ARCH_64.
> ARM64 which is a strong-ordered architecture
I'm not familiar with ARM. it seems to be weakly-ordered?
"Armv8-A implements a weakly-ordered memory architecture."
(https://developer.arm.com/documentation/102336/0100/Memory-ordering)
> /* relaxed read */
> /* relaxed write */
> ..
Other architectures don't use this kind of annotation, so maybe RISC-V
can drop it too.
And DPDK requires a real name in the Signed-off-by line.
