From: Aarnav JP <[email protected]> CPT Completion Queue is supported on CN20K and provides hardware-based completion notification, eliminating the need for software polling. Change the default value of cpt_cq_enable devarg from 0 to 1 so that CPT CQ is enabled by default.
Signed-off-by: Aarnav JP <[email protected]> --- doc/guides/nics/cnxk.rst | 13 +++++++++++++ drivers/net/cnxk/cnxk_ethdev_sec.c | 2 +- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst index 239ebcd05c..c71029e1dc 100644 --- a/doc/guides/nics/cnxk.rst +++ b/doc/guides/nics/cnxk.rst @@ -745,6 +745,19 @@ Runtime Config Options for inline device With the above configuration, inline inbound IPsec post-processing should be done by the application. +- ``Enable CPT Completion Queue for inline IPsec`` (default ``1`` for CN20K, ``0`` otherwise) + + CPT Completion Queue for inline IPsec event delivery can be enabled or disabled + by ``cpt_cq_enable`` devargs parameter. + This option is supported on OCTEON CN20K SoC family. + + For example:: + + -a 0002:1d:00.0,cpt_cq_enable=1 + + With the above configuration, driver would enable CPT completion queue + for inline IPsec event delivery instead of using the err-ring poll thread. + Port Representors ----------------- diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c index fa7eacfbe4..61eb55ba43 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec.c @@ -742,7 +742,7 @@ nix_inl_parse_devargs(struct rte_devargs *devargs, uint32_t meta_buf_sz = 0; uint8_t rx_inj_ena = 0; uint8_t selftest = 0; - uint8_t cpt_cq_enable = 0; + uint8_t cpt_cq_enable = roc_feature_nix_has_cpt_cq_support() ? 1 : 0; memset(&cpt_channel, 0, sizeof(cpt_channel)); -- 2.34.1
