The barrier orders the input ring descriptor write in DMA memory against the MMIO doorbell write. That is device ordering, not SMP ordering: rte_io_wmb() is the correct barrier, and on arm64 the inner shareable dmb the SMP barrier generated was not sufficient to order against the device in the first place.
Signed-off-by: Stephen Hemminger <[email protected]> --- drivers/crypto/caam_jr/caam_jr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/caam_jr/caam_jr.c b/drivers/crypto/caam_jr/caam_jr.c index 1f97e72337..7a345c436e 100644 --- a/drivers/crypto/caam_jr/caam_jr.c +++ b/drivers/crypto/caam_jr/caam_jr.c @@ -1451,7 +1451,8 @@ caam_jr_enqueue_op(struct rte_crypto_op *op, struct caam_jr_qp *qp) /* Set ptr in input ring to current descriptor */ sec_write_addr(&ring->input_ring[ring->pidx], (phys_addr_t)caam_jr_vtop_ctx(ctx, ctx->jobdes.desc)); - rte_smp_wmb(); + /* Descriptor must be visible to the device before the doorbell */ + rte_io_wmb(); /* Notify HW that a new job is enqueued */ hw_enqueue_desc_on_job_ring(ring); -- 2.53.0
