The support for queue_stats_map has been deprecated since 25.11. Remove support for queue mapping in ixgbe driver.
Unlike other drivers where the mapping was a software renumbering, the ixgbe per-queue counters (QPRC/QPTC/QBRC/QBTC/QPRDC) are routed by the RQSMR and TQSM registers which must be programmed after reset. These were previously zeroed at probe, which routes every queue to counter 0, and relied on the application to program a mapping. Program the identity mapping instead, so queue N is counted by counter N without application involvement. DCB still overrides this with its own per traffic class mapping when configured. Signed-off-by: Stephen Hemminger <[email protected]> --- drivers/net/intel/ixgbe/ixgbe_ethdev.c | 123 ++++--------------------- drivers/net/intel/ixgbe/ixgbe_ethdev.h | 9 -- 2 files changed, 19 insertions(+), 113 deletions(-) diff --git a/drivers/net/intel/ixgbe/ixgbe_ethdev.c b/drivers/net/intel/ixgbe/ixgbe_ethdev.c index c5010f623c..d35da73d69 100644 --- a/drivers/net/intel/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/intel/ixgbe/ixgbe_ethdev.c @@ -182,10 +182,6 @@ static int ixgbe_dev_xstats_get_names_by_id( const uint64_t *ids, struct rte_eth_xstat_name *xstats_names, unsigned int limit); -static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, - uint16_t queue_id, - uint8_t stat_idx, - uint8_t is_rx); static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size); static int ixgbe_dev_info_get(struct rte_eth_dev *dev, @@ -511,7 +507,6 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = { .xstats_reset = ixgbe_dev_xstats_reset, .xstats_get_names = ixgbe_dev_xstats_get_names, .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id, - .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set, .fw_version_get = ixgbe_fw_version_get, .dev_infos_get = ixgbe_dev_info_get, .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, @@ -870,109 +865,31 @@ ixgbe_disable_intr(struct ixgbe_hw *hw) } /* - * This function resets queue statistics mapping registers. + * This function programs the queue statistics mapping registers. * From Niantic datasheet, Initialization of Statistics section: * "...if software requires the queue counters, the RQSMR and TQSM registers * must be re-programmed following a device reset. + * + * Each register maps four queues, one 8 bit field per queue, of which only + * the low four bits select one of the IXGBE_QUEUE_STAT_COUNTERS counters. + * Program the identity mapping so that queue N is counted by counter N, + * wrapping for queues beyond the number of available counters. + * + * Note: DCB overrides this with a per traffic class mapping when it is + * configured later in ixgbe_dev_rx_init(). */ static void -ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw) -{ - uint32_t i; - - for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) { - IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0); - IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0); - } -} - - -static int -ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, - uint16_t queue_id, - uint8_t stat_idx, - uint8_t is_rx) -{ -#define QSM_REG_NB_BITS_PER_QMAP_FIELD 8 -#define NB_QMAP_FIELDS_PER_QSM_REG 4 -#define QMAP_FIELD_RESERVED_BITS_MASK 0x0f - - struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); - struct ixgbe_stat_mapping_registers *stat_mappings = - IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private); - uint32_t qsmr_mask = 0; - uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; - uint32_t q_map; - uint8_t n, offset; - - if ((hw->mac.type != ixgbe_mac_82599EB) && - (hw->mac.type != ixgbe_mac_X540) && - (hw->mac.type != ixgbe_mac_X550) && - (hw->mac.type != ixgbe_mac_X550EM_x) && - (hw->mac.type != ixgbe_mac_X550EM_a) && - (hw->mac.type != ixgbe_mac_E610)) - return -ENOSYS; - - PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", - (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", - queue_id, stat_idx); - - n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); - if (n >= IXGBE_NB_STAT_MAPPING_REGS) { - PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); - return -EIO; - } - offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); - - /* Now clear any previous stat_idx set */ - clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); - if (!is_rx) - stat_mappings->tqsm[n] &= ~clearing_mask; - else - stat_mappings->rqsmr[n] &= ~clearing_mask; - - q_map = (uint32_t)stat_idx; - q_map &= QMAP_FIELD_RESERVED_BITS_MASK; - qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); - if (!is_rx) - stat_mappings->tqsm[n] |= qsmr_mask; - else - stat_mappings->rqsmr[n] |= qsmr_mask; - - PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", - (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", - queue_id, stat_idx); - PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, - is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]); - - /* Now write the mapping in the appropriate register */ - if (is_rx) { - PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d", - stat_mappings->rqsmr[n], n); - IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]); - } else { - PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d", - stat_mappings->tqsm[n], n); - IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]); - } - return 0; -} - -static void -ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev) +ixgbe_init_qstat_mappings(struct ixgbe_hw *hw) { - struct ixgbe_stat_mapping_registers *stat_mappings = - IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private); - struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); - int i; + uint32_t i, reg; - /* write whatever was in stat mapping table to the NIC */ - for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) { - /* rx */ - IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]); + RTE_BUILD_BUG_ON(RTE_DIM(((struct ixgbe_hw_stats *)0)->qprc) != 16); - /* tx */ - IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]); + for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) { + /* four queues per register, 8 bits each */ + reg = 0x03020100 + 0x04040404 * (i % 4); + IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); + IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg); } } @@ -1246,8 +1163,8 @@ eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) /* disable interrupt */ ixgbe_disable_intr(hw); - /* reset mappings for queue statistics hw counters*/ - ixgbe_reset_qstat_mappings(hw); + /* program identity mapping for queue statistics hw counters */ + ixgbe_init_qstat_mappings(hw); /* Allocate memory for storing MAC addresses */ eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN * @@ -2742,8 +2659,6 @@ ixgbe_dev_start(struct rte_eth_dev *dev) RTE_BIT64(idx)); } - ixgbe_restore_statistics_mapping(dev); - err = ixgbe_flow_ctrl_enable(dev, hw); if (err < 0) { PMD_INIT_LOG(ERR, "enable flow ctrl err"); diff --git a/drivers/net/intel/ixgbe/ixgbe_ethdev.h b/drivers/net/intel/ixgbe/ixgbe_ethdev.h index 5d3243cb4d..ba826b6d8d 100644 --- a/drivers/net/intel/ixgbe/ixgbe_ethdev.h +++ b/drivers/net/intel/ixgbe/ixgbe_ethdev.h @@ -216,11 +216,6 @@ struct ixgbe_interrupt { uint32_t mask_original; }; -struct ixgbe_stat_mapping_registers { - uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS]; - uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS]; -}; - struct ixgbe_vfta { uint32_t vfta[IXGBE_VFTA_SIZE]; }; @@ -471,7 +466,6 @@ struct ixgbe_adapter { struct rte_eth_fdir_conf fdir_conf; struct ixgbe_hw_fdir_info fdir; struct ixgbe_interrupt intr; - struct ixgbe_stat_mapping_registers stat_mappings; struct ixgbe_vfta shadow_vfta; struct ixgbe_hwstrip hwstrip; struct ixgbe_dcb_config dcb_config; @@ -546,9 +540,6 @@ uint16_t ixgbe_vf_representor_tx_burst(void *tx_queue, struct rte_mbuf **tx_pkts #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \ (&((struct ixgbe_adapter *)adapter)->fdir) -#define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \ - (&((struct ixgbe_adapter *)adapter)->stat_mappings) - #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \ (&((struct ixgbe_adapter *)adapter)->shadow_vfta) -- 2.53.0
