Direct assignment to an atomic variable defaults to sequentially consistent memory order in C11. Since cross-thread memory ordering for packet callback execution and unload is already explicitly enforced by memory barriers, sequentially consistent stores are unnecessary and may emit redundant barrier instructions on weakly ordered architectures.
Update bpf_eth_cbi_inuse() and bpf_eth_cbi_unuse() to use rte_atomic_store_explicit() with rte_memory_order_relaxed, matching the relaxed loads already used in bpf_eth_cbi_wait(). Signed-off-by: Marat Khalili <[email protected]> --- lib/bpf/bpf_pkt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/bpf/bpf_pkt.c b/lib/bpf/bpf_pkt.c index ea7e240494..9dee001f0f 100644 --- a/lib/bpf/bpf_pkt.c +++ b/lib/bpf/bpf_pkt.c @@ -137,7 +137,7 @@ static struct bpf_eth_cbh tx_cbh = { static __rte_always_inline void bpf_eth_cbi_inuse(struct bpf_eth_cbi *cbi) { - cbi->use = BPF_ETH_CBI_INUSE; + rte_atomic_store_explicit(&cbi->use, BPF_ETH_CBI_INUSE, rte_memory_order_relaxed); /* make sure no store/load reordering could happen */ rte_smp_mb(); } @@ -150,7 +150,7 @@ bpf_eth_cbi_unuse(struct bpf_eth_cbi *cbi) { /* make sure all previous loads are completed */ rte_smp_rmb(); - cbi->use = 0; + rte_atomic_store_explicit(&cbi->use, 0, rte_memory_order_relaxed); } /* -- 2.43.0
