AMD General Thank you very much! Then I will use tag x86 and RISCV
> -----Original Message----- > From: Sun Yuechi <[email protected]> > Sent: Tuesday, October 13, 2026 6:40 PM > To: Varghese, Vipin <[email protected]> > Cc: [email protected]; Stephen Hemminger <[email protected]>; > Wathsala Vithanage <[email protected]>; Ajit Khaparde > <[email protected]>; Honnappa Nagarahalli > <[email protected]>; Tummala, Sivaprasad > <[email protected]>; Konstantin Ananyev > <[email protected]>; Bruce Richardson > <[email protected]>; Jan Viktorin <[email protected]>; Morten Brørup > <[email protected]>; Thomas Monjalon <[email protected]>; > David Marchand <[email protected]> > Subject: Re: [PATCH v5 0/3] eal/topology: introduce topology-aware lcore > grouping > > Caution: This message originated from an External Source. Use proper caution > when opening attachments, clicking links, or responding. > > > Hi Vipin, > > Tested v5 on two RISC-V machines, no RISC-V specific code needed. > topology_autotest passes on both. L3 is detected where the firmware describes > it > (SG2044), and empty where it doesn't, same as on ARM. > > Tested-by: Sun Yuechi <[email protected]>
