05/10/2026 09:04, Sun Yuechi: > Patch 1 fixes wrong next hops from a FIB created with > RTE_FIB_F_LOOKUP_NETWORK_ORDER on RISC-V: the vector lookup read the > addresses in host order. > > Patch 2 removes a register spill from the vector lookup loop by > gathering the entries at the width they are stored with. > > Patch 2, ns per lookup, standalone benchmark, tables in cache, -O3: > > 1B 2B 4B 8B > SpacemiT X60 > before 31.1 32.1 30.6 29.7 > after 27.2 27.9 27.6 26.4 > Sophgo SG2044 > before 5.6 5.7 5.9 7.5 > after 4.4 4.1 5.0 6.0 > SpacemiT X100 > before 4.7 4.8 4.8 5.9 > after 4.1 4.2 4.3 5.1 > > fib_perf_autotest, whose addresses miss the cache, gains 0 to 14%. > > Sun Yuechi (2): > fib: fix lookup in network order with RVV > fib: gather entries at their own width with RVV
Applied, thanks.
