2016-07-15 10:30, Chao Zhu: > On weak memory order architecture like POWER, rte_smp_wmb/rte_smp_rmb > need to use CPU instructions, not compiler barrier. This patch fixes > this. Also, to improve performance on PPC64, use light weight sync > instruction instead of sync instruction. > > Signed-off-by: Chao Zhu <chaozhu at linux.vnet.ibm.com>
Applied, thanks