2016-12-16 12:15, Stephen Hemminger: > On Fri, 16 Dec 2016 19:09:02 +0100 > Thomas Monjalon <thomas.monja...@6wind.com> wrote: > > > 2016-12-15 09:26, Stephen Hemminger: > > > On Thu, 15 Dec 2016 12:19:44 +0530 > > > Shreyansh Jain <shreyansh.j...@nxp.com> wrote: > > > > It is not a scale-able model where we have to change eth_driver/eth_dev > > > > for every new device type, other than PCI. Maybe VMBus is _very_ close > > > > to PCI so no changes are required in PCI layer (common, linuxapp, > > > > bsdapp) - but, for others it won't stop there. > > > > > > > > At the least, rte_pci_driver/rte_pci_device should be removed from > > > > eth_driver & rte_eth_dev, respectively - relying on rte_driver and > > > > rte_device. > > > > > > > > This is the primary reason work on the SoC patchset and now the new Bus > > > > model is being done. > > > > > > Agreed. the better long term model is to use C style inheritance where > > > rte_pci_driver has eth_driver inside. > > > The other alternative is to make the second element an opaque pointer. > > > > > > But that was too big a change, and not necessary to get VMBUS to work. > > > Longer term refactoring will take more effort. Go ahead and address it > > > with a better bus model, but that probably isn't going to be ready for > > > a couple of releases. > > > > We'll consider only the approach of generalizing the bus model for integr > > ation. > > Stephen, you are welcome to help make it happen and rebase your work > > on top of this new model. > > Thanks > > I will generalize it to PCI and VMBUS only. I am not inventing a generic SOC > model since that is something that I don't have sufficient knowledge. This > fits the YAGNI principle.
There is already a work in progress to generalize bus handling. It is not specific to SoC design. It is just a better design to add new buses.
