> -----Original Message-----
> From: Richardson, Bruce
> Sent: Tuesday, June 6, 2017 1:42 PM
> To: Ananyev, Konstantin <konstantin.anan...@intel.com>
> Cc: Verkamp, Daniel <daniel.verk...@intel.com>; dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH v2] ring: use aligned memzone allocation
>
> On Tue, Jun 06, 2017 at 10:59:59AM +0100, Ananyev, Konstantin wrote:
> >
> > > >
> > > >
> > > >
> > > > >
> > > > > The PROD/CONS_ALIGN values on x86-64 are set to 2 cache lines, so
> > > > > members
> > > > of struct rte_ring are 128 byte aligned,
> > > > >and therefore the whole struct needs 128-byte alignment according to
> > > > >the ABI
> > > > so that the 128-byte alignment of the fields can be guaranteed.
> > > >
> > > > Ah ok, missed the fact that rte_ring is 128B aligned these days.
> > > > BTW, I probably missed the initial discussion, but what was the reason
> > > > for that?
> > > > Konstantin
> > >
> > > I don't know why PROD_ALIGN/CONS_ALIGN use 128 byte alignment; it seems
> > > unnecessary if the cache line is only 64 bytes. An
> alternate
> > > fix would be to just use cache line alignment for these fields (since
> > > memzones are already cache line aligned).
> >
> > Yes, had the same thought.
> >
> > > Maybe there is some deeper reason for the >= 128-byte alignment logic in
> > > rte_ring.h?
> >
> > Might be, would be good to hear opinion the author of that change.
>
> It gives improved performance for core-2-core transfer.
You mean empty cache-line(s) after prod/cons, correct?
That's ok but why we can't keep them and whole rte_ring aligned on cache-line
boundaries?
Something like that:
struct rte_ring {
...
struct rte_ring_headtail prod __rte_cache_aligned;
EMPTY_CACHE_LINE __rte_cache_aligned;
struct rte_ring_headtail cons __rte_cache_aligned;
EMPTY_CACHE_LINE __rte_cache_aligned;
};
Konstantin
