Previous code only added in AVX, and a few other non-SSE flags to the
compile-time cpuflags because all SSE instruction set levels are now
required for an x86 build. However, some apps may still be checking for the
existing SSE ones in the legacy build system, so add them here for
completeness and compatibility.
Signed-off-by: Bruce Richardson <bruce.richard...@intel.com>
---
config/x86/meson.build | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/config/x86/meson.build b/config/x86/meson.build
index 0d1a532ad..c05c2f418 100644
--- a/config/x86/meson.build
+++ b/config/x86/meson.build
@@ -40,6 +40,12 @@ if cc.get_define('__SSE4_2__', args: march_opt) == ''
error(sse_errormsg)
endif
+base_flags = ['SSE', 'SSE2', 'SSE3','SSSE3', 'SSE4_1', 'SSE4_2']
+foreach f:base_flags
+ dpdk_conf.set('RTE_MACHINE_CPUFLAG_' + f, 1)
+ compile_time_cpuflags += ['RTE_CPUFLAG_' + f]
+endforeach
+
dpdk_conf.set('RTE_ARCH_X86', 1)
if (host_machine.cpu_family() == 'x86_64')
dpdk_conf.set('RTE_ARCH_X86_64', 1)
@@ -66,5 +72,9 @@ if cc.get_define('__AVX2__', args: march_opt) != ''
dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX2', 1)
compile_time_cpuflags += ['RTE_CPUFLAG_AVX2']
endif
+if cc.get_define('__AVX512F__', args: march_opt) != ''
+ dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX512F', 1)
+ compile_time_cpuflags += ['RTE_CPUFLAG_AVX512F']
+endif
dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
--
2.13.5
