viiccwen opened a new issue, #940:
URL: https://github.com/apache/mahout/issues/940

   ### Description
   
   The current batched L2 norm CUDA kernel performs vectorized loads starting 
from input_batch + base, where:
   
   
https://github.com/apache/mahout/blob/d5fc18bd01bd4fbaa6c947252b142f38c9d8b720/qdp/qdp-kernels/src/amplitude.cu#L367C5-L367C49
   
   When sample_len is odd and sample_idx is also odd, base becomes odd, meaning 
input_batch + base is only 8-byte aligned. This violates the alignment 
requirements of vectorized loads: double2 requires 16-byte alignment.
   
   Although this does not cause incorrect results, it introduces avoidable 
performance penalties and makes the kernel’s memory access behavior 
architecture-dependent.
   
   reference: 
[comment](https://github.com/apache/mahout/pull/918#discussion_r2724245973)


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