Hello,
This has come up more than once and just wanted to hash out a design for the
I2C manager driver. Having more than one slave is quite common and the slowest
slave pulls the clock low prohibiting the master from starting another
transaction on the bus.
What we would like to have is :
1. Using the bus while we are waiting for responses from a slave (I assume this
would be a case of clock stretching by the slave)
2. Clock timeout on I2C Bus
3. Read back register writes or Verified register writes
- Multiple register writes will not be supported in this
What do people think about the above features in the I2C Manager and also how
to deal with it ? I have some knowledge of I2C and based on that I can think of
some kind of solution for 2. and 3.. 1 however seems to be a bit complicated
since the nature of I2C is such that it locks up the bus for any future
transactions until the slave makes the clock high. Does anybody have any
possible solutions for this problem ?
Hoping to get answers from the community and get this feature written soon.
Regards,
Vipul Rahane
