yukihiratype2 commented on a change in pull request #22: Add FMC SDRAM for STM32H7x3 chip URL: https://github.com/apache/incubator-nuttx/pull/22#discussion_r362421158
########## File path: arch/arm/src/stm32h7/hardware/stm32_fmc.h ########## @@ -0,0 +1,390 @@ +/************************************************************************************ + * arch/arm/src/stm32h7/hardware/stm32_fmc.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gn...@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FMC_H +#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FMC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_FMC_BCR_OFFSET(n) (8*((n)-1)) +#define STM32_FMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */ +#define STM32_FMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */ +#define STM32_FMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */ +#define STM32_FMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */ + +#define STM32_FMC_BTR_OFFSET(n) (8*((n)-1)+0x0004) +#define STM32_FMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */ +#define STM32_FMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */ +#define STM32_FMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */ +#define STM32_FMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */ + +#define STM32_FMC_BWTR_OFFSET(n) (8*((n)-1)+0x0104) +#define STM32_FMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */ +#define STM32_FMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */ +#define STM32_FMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */ +#define STM32_FMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */ + +#define STM32_FMC_PCR_OFFSET(n) (0x0020*((n)-1)+0x0040) +#define STM32_FMC_PCR2_OFFSET 0x0060 /* NAND Flash/PC Card controller register 2 */ +#define STM32_FMC_PCR3_OFFSET 0x0080 /* NAND Flash/PC Card controller register 3 */ +#define STM32_FMC_PCR4_OFFSET 0x00a0 /* NAND Flash/PC Card controller register 4 */ + +#define STM32_FMC_SR_OFFSET(n) (0x0020*((n)-1)+0x0044) +#define STM32_FMC_SR2_OFFSET 0x0064 /* NAND Flash/PC Card controller register 2 */ +#define STM32_FMC_SR3_OFFSET 0x0084 /* NAND Flash/PC Card controller register 3 */ +#define STM32_FMC_SR4_OFFSET 0x00a4 /* NAND Flash/PC Card controller register 4 */ + +#define STM32_FMC_PMEM_OFFSET(n) (0x0020*((n)-1)+0x0048) +#define STM32_FMC_PMEM2_OFFSET 0x0068 /* Common memory space timing register 2 */ +#define STM32_FMC_PMEM3_OFFSET 0x0088 /* Common memory space timing register 3 */ +#define STM32_FMC_PMEM4_OFFSET 0x00a8 /* Common memory space timing register 4 */ + +#define STM32_FMC_PATT_OFFSET(n) (0x0020*((n)-1)+0x004c) +#define STM32_FMC_PATT2_OFFSET 0x006c /* Attribute memory space timing register 2 */ +#define STM32_FMC_PATT3_OFFSET 0x008c /* Attribute memory space timing register 3 */ +#define STM32_FMC_PATT4_OFFSET 0x00ac /* Attribute memory space timing register 4 */ + +#define STM32_PIO4_OFFSET 0x00b0 /* I/O space timing register 4 */ + +#define STM32_FMC_ECCR_OFFSET(n) (0x0020*((n)-1)+0x003c) +#define STM32_FMC_ECCR2_OFFSET 0x0054 /* ECC result register 2 */ +#define STM32_FMC_ECCR3_OFFSET 0x0074 /* ECC result register 3 */ + +#define STM32_FMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 0 */ +#define STM32_FMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 1 */ + +#define STM32_FMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register, Bank 0 */ +#define STM32_FMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register, Bank 1 */ + +#define STM32_FMC_SDCMR_OFFSET 0x0150 /* SDRAM Config Memory register */ +#define STM32_FMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe */ +#define STM32_FMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */ + +/* Register Addresses ***************************************************************/ + +#define STM32_FMC_BCR(n) (STM32_FMC_BASE+STM32_FMC_BCR_OFFSET(n)) +#define STM32_FMC_BCR1 (STM32_FMC_BASE+STM32_FMC_BCR1_OFFSET ) +#define STM32_FMC_BCR2 (STM32_FMC_BASE+STM32_FMC_BCR2_OFFSET ) +#define STM32_FMC_BCR3 (STM32_FMC_BASE+STM32_FMC_BCR3_OFFSET ) +#define STM32_FMC_BCR4 (STM32_FMC_BASE+STM32_FMC_BCR4_OFFSET ) + +#define STM32_FMC_BTR(n) (STM32_FMC_BASE+STM32_FMC_BTR_OFFSET(n)) +#define STM32_FMC_BTR1 (STM32_FMC_BASE+STM32_FMC_BTR1_OFFSET ) +#define STM32_FMC_BTR2 (STM32_FMC_BASE+STM32_FMC_BTR2_OFFSET ) +#define STM32_FMC_BTR3 (STM32_FMC_BASE+STM32_FMC_BTR3_OFFSET ) +#define STM32_FMC_BTR4 (STM32_FMC_BASE+STM32_FMC_BTR4_OFFSET ) + +#define STM32_FMC_BWTR(n) (STM32_FMC_BASE+STM32_FMC_BWTR_OFFSET(n)) +#define STM32_FMC_BWTR1 (STM32_FMC_BASE+STM32_FMC_BWTR1_OFFSET ) +#define STM32_FMC_BWTR2 (STM32_FMC_BASE+STM32_FMC_BWTR2_OFFSET ) +#define STM32_FMC_BWTR3 (STM32_FMC_BASE+STM32_FMC_BWTR3_OFFSET ) +#define STM32_FMC_BWTR4 (STM32_FMC_BASE+STM32_FMC_BWTR4_OFFSET ) + +#define STM32_FMC_PCR(n) (STM32_FMC_BASE+STM32_FMC_PCR_OFFSET(n)) +#define STM32_FMC_PCR2 (STM32_FMC_BASE+STM32_FMC_PCR2_OFFSET ) +#define STM32_FMC_PCR3 (STM32_FMC_BASE+STM32_FMC_PCR3_OFFSET ) +#define STM32_FMC_PCR4 (STM32_FMC_BASE+STM32_FMC_PCR4_OFFSET ) + +#define STM32_FMC_SR(n) (STM32_FMC_BASE+STM32_FMC_SR_OFFSET(n)) +#define STM32_FMC_SR2 (STM32_FMC_BASE+STM32_FMC_SR2_OFFSET ) +#define STM32_FMC_SR3 (STM32_FMC_BASE+STM32_FMC_SR3_OFFSET ) +#define STM32_FMC_SR4 (STM32_FMC_BASE+STM32_FMC_SR4_OFFSET ) + +#define STM32_FMC_PMEM(n) (STM32_FMC_BASE+STM32_FMC_PMEM_OFFSET(n)) +#define STM32_FMC_PMEM2 (STM32_FMC_BASE+STM32_FMC_PMEM2_OFFSET ) +#define STM32_FMC_PMEM3 (STM32_FMC_BASE+STM32_FMC_PMEM3_OFFSET ) +#define STM32_FMC_PMEM4 (STM32_FMC_BASE+STM32_FMC_PMEM4_OFFSET ) + +#define STM32_FMC_PATT(n) (STM32_FMC_BASE+STM32_FMC_PATT_OFFSET(n)) +#define STM32_FMC_PATT2 (STM32_FMC_BASE+STM32_FMC_PATT2_OFFSET ) +#define STM32_FMC_PATT3 (STM32_FMC_BASE+STM32_FMC_PATT3_OFFSET ) +#define STM32_FMC_PATT4 (STM32_FMC_BASE+STM32_FMC_PATT4_OFFSET ) + +#define STM32_PIO4 (STM32_FMC_BASE+STM32_FMC_PIO4_OFFSET ) + +#define STM32_FMC_ECCR(n) (STM32_FMC_BASE+STM32_FMC_ECCR_OFFSET(n)) +#define STM32_FMC_ECCR2 (STM32_FMC_BASE+STM32_FMC_ECCR2_OFFSET ) +#define STM32_FMC_ECCR3 (STM32_FMC_BASE+STM32_FMC_ECCR3_OFFSET ) + +#define STM32_FMC_SDCR1 (STM32_FMC_BASE+STM32_FMC_SDCR1_OFFSET) +#define STM32_FMC_SDCR2 (STM32_FMC_BASE+STM32_FMC_SDCR2_OFFSET) + +#define STM32_FMC_SDTR1 (STM32_FMC_BASE+STM32_FMC_SDTR1_OFFSET) +#define STM32_FMC_SDTR2 (STM32_FMC_BASE+STM32_FMC_SDTR2_OFFSET) + +#define STM32_FMC_SDCMR (STM32_FMC_BASE+STM32_FMC_SDCMR_OFFSET) +#define STM32_FMC_SDRTR (STM32_FMC_BASE+STM32_FMC_SDRTR_OFFSET) +#define STM32_FMC_SDSR (STM32_FMC_BASE+STM32_FMC_SDSR_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +#define FMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */ +#define FMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */ +#define FMC_BCR_MTYP_SHIFT (2) /* Memory type */ +#define FMC_BCR_MTYP_MASK (3 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_SRAM (0 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_ROM (0 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_PSRAM (1 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_CRAM (1 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_NOR (2 << FMC_BCR_MTYP_SHIFT) +#define FMC_BCR_MWID_SHIFT (4) /* Memory data bus width */ +#define FMC_BCR_MWID_MASK (3 << FMC_BCR_MWID_SHIFT) +# define FMC_BCR_MWID8 (0 << FMC_BCR_MWID_SHIFT) +# define FMC_BCR_MWID16 (1 << FMC_BCR_MWID_SHIFT) +#define FMC_BCR_FACCEN (1 << 6) /* Flash access enable */ +#define FMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */ +#define FMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */ +#define FMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */ +#define FMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */ +#define FMC_BCR_WREN (1 << 12) /* Write enable bit */ +#define FMC_BCR_WAITEN (1 << 13) /* Wait enable bit */ +#define FMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */ +#define FMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */ +#define FMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */ +#define FMC_BCR_BMAP_SHIFT (24) +# define FMC_BCR_BMAP_0 (0 << FMC_BCR_BMAP_SHIFT) +# define FMC_BCR_BMAP_1 (1 << FMC_BCR_BMAP_SHIFT) +# define FMC_BCR_BMAP_2 (2 << FMC_BCR_BMAP_SHIFT) Review comment: No, that's my fault. I should check before push ---------------------------------------------------------------- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. For queries about this service, please contact Infrastructure at: us...@infra.apache.org With regards, Apache Git Services
