In case it already got through, sorry :)
---------- Forwarded message ---------
From: Reto Gähwiler <gret.hexa...@gmail.com>
Date: Mon, 2 Mar 2020 at 10:16
Subject: [PATCH] stm32h7/f30 register updates, typos and a Tcpinput bug fix
To: <dev@nuttx.apache.org>
Hey there,
attached are 4 patch files with the following fixes:
* net/Tcp/Tcpinput: in case of a keepAlive sequence number is
incremented, removed that
* stm32h7_phy_boardinitialize: changed placement of this call to ensure
that it can be used to take phy out of reset/power enable before an
ethernet reset is done
* stm32h7 / stm32f30: register extension and/or fixes, typo
* stm32h7_ethernet.c: fixed freeframe so that all segments will be
released, could end up in entire lock down of ethernet
For the last one see also this discussion:
https://lists.apache.org/thread.html/845d6f8103f126afe875d2827186186480341a3ffca3e15e670feb4f%40%3Cdev.nuttx.apache.org%3E
Cheers, Reto
From b76649ae2d4a585a28e22534ecf5627c3e4e7709 Mon Sep 17 00:00:00 2001
From: GAEHWILER Reto <reto.gaehwiler@hexagon.com>
Date: Fri, 28 Feb 2020 16:37:57 +0100
Subject: [PATCH] STM32H7 fix for network lock downs due to not freed buffers
* https://lists.apache.org/thread.html/r18cd4bfcf7631119906d744bbabf28e256904555dbc05ba02aef4fd2%40%3Cdev.nuttx.apache.org%3E
* added descrpitor size to kconfig
* corrected some typos
---
arch/arm/src/stm32h7/Kconfig | 12 +++++++++++
arch/arm/src/stm32h7/stm32_ethernet.c | 31 ++++++++++++---------------
2 files changed, 26 insertions(+), 17 deletions(-)
diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig
index 3c07db34a3..355d06064f 100644
--- a/arch/arm/src/stm32h7/Kconfig
+++ b/arch/arm/src/stm32h7/Kconfig
@@ -4459,6 +4459,18 @@ config STM32H7_AUTONEG
---help---
Use PHY autonegotiation to determine speed and mode
+config STM32H7_ETH_NRXDESC
+ int "Number of RX descriptors"
+ default 8
+ ---help---
+ Number of RX DMA descriptors to use.
+
+config STM32H7_ETH_NTXDESC
+ int "Number of TX descriptors"
+ default 4
+ ---help---
+ Number of TX DMA descriptors to use.
+
config STM32H7_ETHFD
bool "Full duplex"
default n
diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c
index d9903cf615..b33c84a20f 100644
--- a/arch/arm/src/stm32h7/stm32_ethernet.c
+++ b/arch/arm/src/stm32h7/stm32_ethernet.c
@@ -216,7 +216,7 @@
#endif
#if ETH_BUFSIZE != OPTIMAL_ETH_BUFSIZE
-# warning "You using an incomplete/untested configuration"
+# warning "You are using an incomplete/untested configuration"
#endif
#ifndef CONFIG_STM32H7_ETH_NRXDESC
@@ -230,7 +230,7 @@
#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32H7_ETH_NTXDESC+1)
-/* Buffers use for DMA access must begin on an address aligned with the
+/* Buffers used for DMA access must begin on an address aligned with the
* D-Cache line and must be an even multiple of the D-Cache line size.
* These size/alignment requirements are necessary so that D-Cache flush
* and invalidate operations will not have any additional effects.
@@ -1222,7 +1222,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
*/
up_clean_dcache((uintptr_t)txdesc,
- (uintptr_t)txdesc + sizeof(struct eth_desc_s));
+ (uintptr_t)txdesc + sizeof(struct eth_desc_s));
/* Point to the next available TX descriptor */
@@ -1601,15 +1601,15 @@ static void stm32_freesegment(struct stm32_ethmac_s *priv,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct eth_desc_s));
- /* Update the tail pointer */
-
- stm32_putreg((uintptr_t)rxdesc, STM32_ETH_DMACRXDTPR);
-
/* Get the next RX descriptor in the chain (cache coherency should not
* be an issue because the link address is constant.
*/
rxdesc = stm32_get_next_rxdesc(priv, rxdesc);
+
+ /* Update the tail pointer */
+
+ stm32_putreg((uintptr_t)rxdesc, STM32_ETH_DMACRXDTPR);
}
/* Reset the segment management logic */
@@ -1621,7 +1621,9 @@ static void stm32_freesegment(struct stm32_ethmac_s *priv,
if ((stm32_getreg(STM32_ETH_DMACSR) & ETH_DMACSR_RBU) != 0)
{
- /* TODO: This is probably not needed at all? */
+ /* Clear the RBU flag */
+
+ stm32_putreg(ETH_DMACSR_RBU, STM32_ETH_DMACSR);
nerr("ETH_DMACSR_RBU\n");
@@ -1694,7 +1696,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
/* Forces the first RX descriptor to be re-read from physical memory */
up_invalidate_dcache((uintptr_t)rxdesc,
- (uintptr_t)rxdesc + sizeof(struct eth_desc_s));
+ (uintptr_t)rxdesc + sizeof(struct eth_desc_s));
for (i = 0;
(rxdesc->des3 & ETH_RDES3_WB_OWN) == 0 &&
@@ -2068,14 +2070,9 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv)
DEBUGASSERT(txdesc->des0 != 0);
- /* Check if this is the first segment of a TX frame. */
+ /* Yes.. Free the buffer */
- if ((txdesc->des3 & ETH_TDES3_RD_FD) != 0)
- {
- /* Yes.. Free the buffer */
-
- stm32_freebuffer(priv, (uint8_t *)txdesc->des0);
- }
+ stm32_freebuffer(priv, (uint8_t *)txdesc->des0);
/* In any event, make sure that des0-3 are nullified. */
@@ -2101,7 +2098,7 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv)
priv->inflight--;
/* If all of the TX descriptors were in-flight, then RX
- * interruptsmay have been disabled... we can re-enable them
+ * interrupts may have been disabled... we can re-enable them
* now.
*/
--
2.17.1
From bc89fa221b1bc8cfec862338465345a2b9a4b682 Mon Sep 17 00:00:00 2001
From: GAEHWILER Reto <reto.gaehwiler@hexagon.com>
Date: Fri, 28 Feb 2020 16:47:25 +0100
Subject: [PATCH] STM32H7 re-organization of stm32_phy_boardinitialize
* phy has to be up and running before ethreset call
---
arch/arm/src/stm32h7/stm32_ethernet.c | 33 ++++++++++++++++++---------
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c
index d9903cf615..6cd9f19963 100644
--- a/arch/arm/src/stm32h7/stm32_ethernet.c
+++ b/arch/arm/src/stm32h7/stm32_ethernet.c
@@ -3473,17 +3473,6 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
stm32_phyregdump();
#endif
- /* Perform any necessary, board-specific PHY initialization */
-
-#ifdef CONFIG_STM32H7_PHYINIT
- ret = stm32_phy_boardinitialize(0);
- if (ret < 0)
- {
- nerr("ERROR: Failed to initialize the PHY: %d\n", ret);
- return ret;
- }
-#endif
-
/* Special workaround for the Davicom DM9161 PHY is required. */
#ifdef CONFIG_ETH0_PHY_DM9161
@@ -4260,6 +4249,17 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv)
* sequence in stm32_rcc.c.
*/
+ /* Perform any necessary, board-specific PHY initialization */
+
+#ifdef CONFIG_STM32H7_PHYINIT
+ ret = stm32_phy_boardinitialize(0);
+ if (ret < 0)
+ {
+ nerr("ERROR: Failed to initialize the PHY: %d\n", ret);
+ return ret;
+ }
+#endif
+
/* Initialize the free buffer list */
stm32_initbuffer(priv, &g_txbuffer[priv->intf * TXBUFFER_SIZE]);
@@ -4377,6 +4377,17 @@ int stm32_ethinitialize(int intf)
return -EAGAIN;
}
+ /* Perform any necessary, board-specific PHY initialization */
+
+#ifdef CONFIG_STM32H7_PHYINIT
+ ret = stm32_phy_boardinitialize(0);
+ if (ret < 0)
+ {
+ nerr("ERROR: Failed to initialize the PHY: %d\n", ret);
+ return ret;
+ }
+#endif
+
/* Put the interface in the down state. */
stm32_ifdown(&priv->dev);
--
2.17.1
From 6cff2b04970a1467c02a459fdc56cd046d3587c4 Mon Sep 17 00:00:00 2001
From: GAEHWILER Reto <reto.gaehwiler@hexagon.com>
Date: Fri, 28 Feb 2020 16:55:09 +0100
Subject: [PATCH] Fix of faulty TCP sequence increments in net/tcp/tcp_input.c
* sequence numbers must not be incremented in case of retransmitted packets
---
net/tcp/tcp_input.c | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/net/tcp/tcp_input.c b/net/tcp/tcp_input.c
index 1b86e7dfbc..3daf251293 100644
--- a/net/tcp/tcp_input.c
+++ b/net/tcp/tcp_input.c
@@ -430,16 +430,7 @@ found:
if (ackseq < rcvseq)
{
- if (dev->d_len > 0)
- {
- /* Increment the received sequence number (perhaps including the
- * discarded dummy byte in the probe).
- */
-
- net_incr32(conn->rcvseq, dev->d_len);
- }
-
- /* And send a "normal" acknowledgment of the KeepAlive probe */
+ /* Send a "normal" acknowledgment of the KeepAlive probe */
tcp_send(dev, conn, TCP_ACK, tcpiplen);
return;
--
2.17.1
From b1b30cbfd5115328c7c0cc045c6fafeb263bdb5e Mon Sep 17 00:00:00 2001
From: GAEHWILER Reto <reto.gaehwiler@hexagon.com>
Date: Mon, 2 Mar 2020 09:19:54 +0100
Subject: [PATCH] Typos, register correction and extension
* correction in stm32h7x3xx_rcc
* adding GPIO_TIM2_CH1OUT_1 to stm32f30xxx_pinmap
* docu typo fix in drivers/mmcsd/mmcsd_spi.c
---
arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h | 1 +
arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h | 15 ++++++++-------
drivers/mmcsd/mmcsd_spi.c | 2 +-
3 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h b/arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h
index aca2a27918..2a7abf2a0a 100644
--- a/arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h
@@ -302,6 +302,7 @@
#define GPIO_TIM2_CH1_ETR_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
#define GPIO_TIM2_CH1_ETR_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN5)
#define GPIO_TIM2_CH1_ETR_4 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN3)
+#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
#define GPIO_TIM2_CH2IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM2_CH2IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
index dacd1edb17..dcd0f236e0 100644
--- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
@@ -263,18 +263,19 @@
# define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 000: HSI clock selected */
# define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 001: LSE oscillator selected */
# define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 010: HSE oscillator clock selected */
-# define RCC_CFGR_MCO1_PLL (3 << RCC_CFGR_MCO1_SHIFT) /* 011: PLL clock selected */
+# define RCC_CFGR_MCO1_PLL1Q (3 << RCC_CFGR_MCO1_SHIFT) /* 011: PLL clock selected */
# define RCC_CFGR_MCO1_HSI48 (4 << RCC_CFGR_MCO1_SHIFT) /* 100: HSI48 clock selected */
#define RCC_CFGR_MCO2PRE_SHIFT (25) /* Bits 25-28: MCO2 prescaler */
#define RCC_CFGR_MCO2PRE_MASK (0xf << RCC_CFGR_MCO2PRE_SHIFT)
# define RCC_CFGR_MCO2PRE(x) (((uint32_t)(x)) << RCC_CFGR_MCO2PRE_SHIFT)
#define RCC_CFGR_MCO2_SHIFT (29) /* Bits 29-31: Microcontroller Clock Output 2 */
-#define RCC_CFGR_MCO2_MASK (7 << RCC_CFGR_MCO1_SHIFT)
-# define RCC_CFGR_MCO2_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 000: HSI clock selected */
-# define RCC_CFGR_MCO2_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 001: LSE oscillator selected */
-# define RCC_CFGR_MCO2_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 010: HSE oscillator clock selected */
-# define RCC_CFGR_MCO2_PLL (3 << RCC_CFGR_MCO1_SHIFT) /* 011: PLL clock selected */
-# define RCC_CFGR_MCO2_HSI48 (4 << RCC_CFGR_MCO1_SHIFT) /* 100: HSI48 clock selected */
+#define RCC_CFGR_MCO2_MASK (7 << RCC_CFGR_MCO2_SHIFT)
+# define RCC_CFGR_MCO2_SYS (0 << RCC_CFGR_MCO2_SHIFT) /* 000: HSI clock selected */
+# define RCC_CFGR_MCO2_PLL2P (1 << RCC_CFGR_MCO2_SHIFT) /* 001: PLL2 peripheral clock selected */
+# define RCC_CFGR_MCO2_HSE (2 << RCC_CFGR_MCO2_SHIFT) /* 010: HSE oscillator clock selected */
+# define RCC_CFGR_MCO2_PLL1P (3 << RCC_CFGR_MCO2_SHIFT) /* 011: PLL1 peripheral clock selected */
+# define RCC_CFGR_MCO2_CSI (4 << RCC_CFGR_MCO2_SHIFT) /* 100: CSI clock selected */
+# define RCC_CFGR_MCO2_LSI (5 << RCC_CFGR_MCO2_SHIFT) /* 101: LSI clock selected */
/* Bit definitions for RCC_D1CFGR */
diff --git a/drivers/mmcsd/mmcsd_spi.c b/drivers/mmcsd/mmcsd_spi.c
index 48553e8565..5161b4e000 100644
--- a/drivers/mmcsd/mmcsd_spi.c
+++ b/drivers/mmcsd/mmcsd_spi.c
@@ -265,7 +265,7 @@ static struct mmcsd_slot_s g_mmcsdslot[CONFIG_MMCSD_NSLOTS];
static const uint32_t g_transpeedru[8] =
{
- 10000, /* 0: 10 Kbit/sec / 10 */
+ 10000, /* 0: 100 Kbit/sec / 10 */
100000, /* 1: 1 Mbit/sec / 10 */
1000000, /* 2: 10 Mbit/sec / 10 */
10000000, /* 3: 100 Mbit/sec / 10 */
--
2.17.1
