On Fri, Jan 26, 2024 at 8:40 PM Alan C. Assis wrote: > His toolchain is focused on FPGA, but he is interested in participating in > other projects for GSoC.
Yes, and that toolchain could be used to cross-build NuttX ROTS to FPGA without a CPU with amazing efficiency as proved on x86 architecture! This is something unique and soon technology will probably enable rapid ASIC prototyping we could have a working solution like no one else. Look at NeuraLink their only way because of energy and size is the ASIC way. More companies will follow in upcoming years because everything becomes smaller and more energy efficient.. soon it will probably harvest power from the air. I think this is worth considering and Victor is keen to use his experience in this area :-) By the way what is this GSOC about? Do they provide a funding for a given research? Do all proposals are accepted? What is the timeline? I always wanted to make smart debug probe fully open-source now I know it will be done on NuttX.. maybe OpenOCD could be ported here and run from ESP32-S3 (it is cheap, has USB-JTAG, WIFI, BLE, and fast GPIO)? :-) I just give ideas as requested :D > Also we need NuttX mentors, I will participate, but for each project we > need two mentors, please let me know who could be interested to help. I would gladly help but my experience is still to small to mentor sorry :-( I think Lup would be a great mentor.. if that does not prevent him from taking part in the projects?? -- CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
