I think a useful application could be in some microprocessors like Allwinner A10, A13, etc.
It could be possible to create a board without DDR memory and use the internal cache as SRAM memory. For example A13 is low cost: https://aliexpress.com/item/1005001719371194.html has an easy to solder package and is more powerful than almost all MCUs. BR, Alan On Wed, May 21, 2025 at 6:42 PM Tomek CEDRO <to...@cedro.info> wrote: > Thank you Alan, this is a nice read, and it touches Cache as RAM > (CAR), while I was thinking about putting whole RTOS inside cache :D > L1 cache is the fastest memory possible, faster than L2, and a lot > faster than DRAM/SRAM, that is faster than any storage drive :-) Just > a curiosity :-) > Tomek > > On Wed, May 21, 2025 at 10:34 PM Alan C. Assis <acas...@gmail.com> wrote: > > > > Hi Tomek, > > > > Yes, it is possible, coreboot (LinuxBIOS) did it more than 20 years ago: > > > https://web.archive.org/web/20200530213938/https://www.coreboot.org/images/6/6c/LBCar.pdf > > > > But since the computer normally will have DDR memory in the board, there > is > > not much motivation to do it for NuttX. > > > > BR, > > > > Alan > > > > On Wed, May 21, 2025 at 4:49 PM Tomek CEDRO <to...@cedro.info> wrote: > > > > > Hello world :-) > > > > > > This post on LinkedIn by Laurie Laurie Kirk inspired me, as I know > > > Raiden is working on x86/AMD64 port of NuttX, and I have recenlty > > > upgraded my main desktop to Intel Ultra9 285K that has 36 MB Intel > > > Smart Cache / 40MB L2 Cache. Maybe a nice challenge to see it NuttX > > > can run entirely from CPU Cache too as we run it on MCUs below 16KB > > > Flash and 8KB RAM? :-) > > > > > > What if an OS fit entirely inside the CPU’s Cache? > > > > > > Turns out we’ve been doing it for decades. CNK, the OS for IBM’s Blue > > > Gene Supercomputer, is just 5,000 lines of tight C++. > > > > > > Designed to “eliminate OS noise”, it lives in the cache after just a > > > few milliseconds of boot. > > > > > > — > > > > > > Kernels that “live” in the cache are common for HPC. > > > > > > Cray’s Catamount microkernel (~2005) used a similar method for jitter > > > free timing. > > > > > > Huge Pages, Statically Mapped Memory, and a lack of scheduling are all > > > typical aspects of these systems. > > > > > > What about the modern era? > > > > > > — > > > > > > Modern CPUs are *insane*. > > > > > > L3 sizes exceed GIGABYTES per socket (see Genoa). > > > > > > Many HPC labs run the hot path in light kernels (LWKs), outsourcing > > > file I/O and syscalls to separate nodes; all with the intent of > > > reducing µs-level jitter. Determinism is the name of the game. > > > > > > — > > > > > > Fujitsu uses 48 LWK cores for every 2 “assistant” Linux cores in their > > > Fugaku supercomputer. > > > > > > Sandia prefers Linux (RHEL), but special queues request their > > > homegrown LWK “Kitten”. > > > > > > In the OSS world, projects like HermitCore and Unikraft see > > > experimentation in the Cloud space. > > > > > > -- > > > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info > > > > > > > -- > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info >
