All,
I'm working on adding stm32h753zi HW hash acceleration and the crypto
API at https://nuttx.apache.org/docs/latest/components/crypto.html does
not mention any restrictions on buffer alignment or sizes.
The question I have is whether it underlying HW hash acceleration is
required to handle oddball alignment/sizes of multiple buffers hashed in
a single crypt session.
To investigate I extended the hash test program by adding unaligned
buffer size tests that for each hash type hashes multiple unaligned
buffer sizes in one session (e.g. call ioctl(CIOCCRYPT) with a 1-byte
buffer, and again with a 2-byte buffer and a third time with a 3-byte
buffer), then call syshash_finish() to generate a digest, comparing the
result with the same generated by a single call to ioctl(CIOCCRYPT) over
a 6-byte buffer containing a concatenation of the three buffers used
above. The software crypto implementation has no problem handling
unaligned buffer sizes.
Should cryptodev device implementations handle unaligned buffer sizes?
Thanks in advance!
--
Peter Barada
[email protected]
