Dear NuttX Community, This is a follow-up to my initial announcement on August 6, 2025 (https://www.mail-archive.com/[email protected]/msg14861.html).
First, I would like to thank Tomek CEDRO for the prompt and encouraging reply. I apologize for the delayed follow-up — my university email does not reliably receive list replies. I will continue sending from this address, but kindly request that replies also CC my personal email: [email protected], so that I do not miss any further communication. Since the initial announcement, I have significantly extended the BSP and completed all planned peripherals: Additional Drivers Completed: ----------------------------- - USBHS (Device and Host modes, fully functional) - CORDIC (hardware accelerated math) - SDMMC (ADMA2 supported, FATFS verified) All drivers have been tested on hardware (600 MHz, Cache disabled due to SIP Flash limitation). A complete test log (boot, ostest, CoreMark, mtd, sdbench, ramspeed, osperf, pi_css5) is available at: https://github.com/Felix-LJY/nuttx/blob/felix-liao/arch/arm/src/n32h7/nuttx_test.log Key Benchmark Highlights: ------------------------- CoreMark: 2358.861456 (3.93 CoreMark/MHz) Reference: STM32H750 @ 480 MHz ~1588 (~3.31 CoreMark/MHz) MTD Flash (/dev/mtd0): Write: 1689.77 KiB/s | Read: 22755.56 KiB/s | Verification: PASSED SDMMC (sdbench, block size 4096): Sequential Write: 1423.2 KB/s | Sequential Read: 4728.1 KB/s OS Performance (osperf, 100 iterations, units in DWT cycles): context-switch: 724 | pthread-create: 12330 | semwait: 85 ostest: All tests PASSED ramspeed: memcpy/memset bandwidth validated pi_css5: 32768 digits of PI in 0.72 seconds (verified on FATFS) /proc/cpuinfo: ARMv7-M rev 2, 600 MHz Commit History (38,889 lines net increment, excluding merge commit): -------------------------------------------------------------------- The work was developed across 6 logical commits (merge commit f122931d0830 excluded from the final patch series): 1. 2f74095b9009 : Add chip n32h762 and devkit board skeleton (initial Kconfig, chip.h, irq.h, memorymap, driver stubs) 2. de39b210e8d1 : Add capture, flash, and USBHS (developing) (n32_capture, n32_flash, n32_usbhsdev/host) 3. 23a695eec8a8 : USBHS device mode porting completed 4. 9d675076c512 : USBHS host, CORDIC, CoreMark completed; SDMMC development started 5. 98d7392ec3bd : SDMMC in progress (driver refinements) 6. c4b493bf3696 : SDMMC completed with ADMA2 support; sdbench verified (1.3 MB/s WR, 4.7 MB/s RD) I am currently resolving all checkpatch warnings and will include a final cleanup commit before submitting the PR. Questions for the Community: ----------------------------- 1. Documentation: Should I add a new page under Documentation/platforms/arm/n32h7/? Are there specific template requirements? 2. Testing Logs: Full logs are available at the GitHub link above. Is this format acceptable, or do you prefer logs included inline or linked externally? 3. Patch Granularity: Is the 6-commit split acceptable, or do you prefer finer granularity? Should I submit a Draft PR for early review? The code compiles with zero warnings on both GCC (15+) and Clang (19+). Thank you for your time and guidance. I look forward to your feedback. Best regards, Felix LIAO (JingYue LIAO) Southwest Jiaotong University GitHub: Felix-LJY
