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https://issues.apache.org/jira/browse/DISPATCH-1372?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel&focusedCommentId=16869650#comment-16869650
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Francesco Nigro commented on DISPATCH-1372:
-------------------------------------------

I've performed some load tests with 9 pairs getting ~64 K msg/sec x 9 = 576 K 
msg/sec
vs master = 52 K msg/sec  x 9 =  468 K msg/sec

The improvement is already there, need to find out which adjustments could be 
done to improve it further:
* fields of chunks to be reordered
* configurable CHUNK_SIZE
* queue-like access pattern instead of stack

> alloc_pool intrusive linked list can be replaced by a linked stack
> ------------------------------------------------------------------
>
>                 Key: DISPATCH-1372
>                 URL: https://issues.apache.org/jira/browse/DISPATCH-1372
>             Project: Qpid Dispatch
>          Issue Type: Improvement
>          Components: Routing Engine
>    Affects Versions: 1.8.0
>            Reporter: Francesco Nigro
>            Priority: Major
>         Attachments: DOOM-3-BFG-Technical-Note.pdf, 
> image-2019-06-21-11-08-17-015.png, image-2019-06-21-11-09-02-228.png, 
> linked_list_misses.svg, stack_list_misses.svg
>
>
> alloc_pool is currently using a intrusive linked list approach to reduce the 
> need of external data structures to hold data, saving expensive pointer 
> chasing, but on modern architectures the data dependency between a current 
> node and next/prev prevent the CPU prefetcher to stream nodes speculatively.
> There are different approaches that could benefit of prefetcing, but need to 
> decouple the data stored from its container eg a linked stack.
> A linked stack is composed by doubly-linked chunks (allocated lazily) that 
> make possible for the CPU to prefetch next/prev pointers given that those are 
> already contained in the current chunk (if any).
> Although it seems counter-intuitive (given that introduce 1 more hop to reach 
> the data), such data-structure is much more cache-friendly on modern 
> architectures: I will attach some cache misses analysis to show it.
>  



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