ring buffer optimization is common and critical on dsp(or other VLIW-like Asic). Except tvm framwork can support this.
https://discuss.tvm.ai/t/questions-about-memory-latency-hiding-on-dsp/1843 --- [Visit Topic](https://discuss.tvm.ai/t/tensor-expression-add-hardware-specific-schedule/1893/16) to respond. You are receiving this because you enabled mailing list mode. To unsubscribe from these emails, [click here](https://discuss.tvm.ai/email/unsubscribe/e447da15c2bfd934a86433386513b80bbe5dbdf70f6ae112c15082b6cffdbec3). Tianqi Chen, UW, Seattle, WA, 98105, United States http://tracking.discuss.tvm.ai/tracking/unsubscribe?msgid=VNDwTNizO7044pTar0KtWg2
