On Thu, 16 May 2019 at 16:22, Marcin Wojtas <m...@semihalf.com> wrote: > > Hi Ard, > > czw., 16 maj 2019 o 16:16 Ard Biesheuvel <ard.biesheu...@linaro.org> > napisaĆ(a): > > > > On Thu, 9 May 2019 at 11:54, Marcin Wojtas <m...@semihalf.com> wrote: > > > > > > Wire up the platform libraries to the generic drivers so that we can use > > > PCI devices and UEFI, and leave the controller initialized so that the > > > OS can boot it using a generic driver of its own. > > > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > > Signed-off-by: Marcin Wojtas <m...@semihalf.com> > > > --- > > > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 17 +++++++++++++++-- > > > Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 5 +++++ > > > 2 files changed, 20 insertions(+), 2 deletions(-) > > > > > > diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > > > b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > > > index 545b369..f78a76b 100644 > > > --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > > > +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > > > @@ -70,8 +70,10 @@ > > > IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf > > > > > > UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf > > > CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf > > > - PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf > > > - PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf > > > + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf > > > + > > > PciHostBridgeLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.inf > > > + > > > PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf > > > + > > > PciExpressLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf > > > > > > # Basic UEFI services libraries > > > UefiLib|MdePkg/Library/UefiLib/UefiLib.inf > > > @@ -407,6 +409,12 @@ > > > > > > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000 > > > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 > > > > > > + # PCIE > > > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 > > > + > > > + # SoC Configuration Space > > > + gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xE0000000 > > > + > > > !if $(CAPSULE_ENABLE) > > > [PcdsDynamicExDefault.common.DEFAULT] > > > > > > gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100 > > > @@ -520,6 +528,11 @@ > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf > > > Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonDxe.inf > > > > > > + # PCI > > > + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf > > > > This driver requires gArmTokenSpaceGuid.PcdPciIoTranslation to be set > > to a sane value. Are you sure this is the case for your platforms? > > > > Do you mean the IO space for the controller? If yes, I'll set the PCD > to according value I use in board description. I don't have an old > enough endpoint that requires IO space to test :) >
Yes, it is basically the MMIO address of the I/O space. Leif kindly gave me a PCIe serial port controller that I use especially for testing these things at plugfests. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#40802): https://edk2.groups.io/g/devel/message/40802 Mute This Topic: https://groups.io/mt/31553481/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-