On 5/29/19 5:12 PM, Laszlo Ersek wrote: > This reverts commit 75136b29541b0e093a51d2e2c2af8d19855c2b60. > > The original fix for <https://bugzilla.tianocore.org/show_bug.cgi?id=1814> > triggered a bug / incorrect assumption in QEMU. > > QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above > it. When the firmware doesn't satisfy this assumption, QEMU generates an > \_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the > firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign > 32-bit MMIO BARs. > > Working around the problem in the firmware looks less problematic than > fixing QEMU. Revert the original changes first, before implementing an > alternative fix. > > Cc: Ard Biesheuvel <ard.biesheu...@linaro.org> > Cc: Gerd Hoffmann <kra...@redhat.com> > Cc: Jordan Justen <jordan.l.jus...@intel.com> > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859 > Signed-off-by: Laszlo Ersek <ler...@redhat.com>
Reviewed-by: Philippe Mathieu-Daude <phi...@redhat.com> > --- > OvmfPkg/OvmfPkgIa32.dsc | 5 ++++- > OvmfPkg/OvmfPkgIa32X64.dsc | 5 ++++- > OvmfPkg/OvmfPkgX64.dsc | 5 ++++- > OvmfPkg/PlatformPei/Platform.c | 9 +++++---- > 4 files changed, 17 insertions(+), 7 deletions(-) > > diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc > index b3446ece311a..578fc6c98ec8 100644 > --- a/OvmfPkg/OvmfPkgIa32.dsc > +++ b/OvmfPkg/OvmfPkgIa32.dsc > @@ -490,7 +490,10 @@ [PcdsFixedAtBuild] > # This PCD is used to set the base address of the PCI express hierarchy. It > # is only consulted when OVMF runs on Q35. In that case it is programmed > into > # the PCIEXBAR register. > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 > + # > + # On Q35 machine types that QEMU intends to support in the long term, QEMU > + # never lets the RAM below 4 GB exceed 2 GB. > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 > > !ifdef $(SOURCE_DEBUG_ENABLE) > gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 > diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc > index 679d4eb8dd36..eade8f62d3de 100644 > --- a/OvmfPkg/OvmfPkgIa32X64.dsc > +++ b/OvmfPkg/OvmfPkgIa32X64.dsc > @@ -495,7 +495,10 @@ [PcdsFixedAtBuild] > # This PCD is used to set the base address of the PCI express hierarchy. It > # is only consulted when OVMF runs on Q35. In that case it is programmed > into > # the PCIEXBAR register. > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 > + # > + # On Q35 machine types that QEMU intends to support in the long term, QEMU > + # never lets the RAM below 4 GB exceed 2 GB. > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 > > !ifdef $(SOURCE_DEBUG_ENABLE) > gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 > diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc > index 56a9560262aa..733a4c9d8a43 100644 > --- a/OvmfPkg/OvmfPkgX64.dsc > +++ b/OvmfPkg/OvmfPkgX64.dsc > @@ -495,7 +495,10 @@ [PcdsFixedAtBuild] > # This PCD is used to set the base address of the PCI express hierarchy. It > # is only consulted when OVMF runs on Q35. In that case it is programmed > into > # the PCIEXBAR register. > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 > + # > + # On Q35 machine types that QEMU intends to support in the long term, QEMU > + # never lets the RAM below 4 GB exceed 2 GB. > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 > > !ifdef $(SOURCE_DEBUG_ENABLE) > gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 > diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c > index fd8eccaf3e50..9c013613a1a0 100644 > --- a/OvmfPkg/PlatformPei/Platform.c > +++ b/OvmfPkg/PlatformPei/Platform.c > @@ -184,13 +184,14 @@ MemMapInitialization ( > PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; > if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { > // > - // The 32-bit PCI host aperture is expected to fall between the top of > - // low RAM and the base of the MMCONFIG area. > + // The MMCONFIG area is expected to fall between the top of low RAM and > + // the base of the 32-bit PCI host aperture. > // > PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress); > - ASSERT (PciBase < PciExBarBase); > + ASSERT (TopOfLowRam <= PciExBarBase); > ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB); > - PciSize = (UINT32)(PciExBarBase - PciBase); > + PciBase = (UINT32)(PciExBarBase + SIZE_256MB); > + PciSize = 0xFC000000 - PciBase; > } else { > PciSize = 0xFC000000 - PciBase; > } > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41635): https://edk2.groups.io/g/devel/message/41635 Mute This Topic: https://groups.io/mt/31834716/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-