Reviewed-by: Nate DeSimone <nathaniel.l.desim...@intel.com> -----Original Message----- From: Chiu, Chasel Sent: Friday, May 31, 2019 4:42 AM To: devel@edk2.groups.io Cc: Chiu, Chasel <chasel.c...@intel.com>; Kubacki, Michael A <michael.a.kuba...@intel.com>; Chaganty, Rangasai V <rangasai.v.chaga...@intel.com>; Desimone, Nathaniel L <nathaniel.l.desim...@intel.com> Subject: [PATCH 2/2] KabylakeOpenBoardPkg: Support DynamicExPCD from FSP.
From: "Chasel, Chiu" <chasel.c...@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1864 Cleaned up unused PciExpress related PCD from INF and remove unnecessary DEFINE from DSC. Defines some PCDs as different types per API mode or Dispatch mode, also enlarge PeiMemory for Dispatch mode as both FSP and boot loader shares the same PeiMemory. Test: Boot with FSP API mode successfully. Cc: Michael A Kubacki <michael.a.kuba...@intel.com> Cc: Sai Chaganty <rangasai.v.chaga...@intel.com> Cc: Nate DeSimone <nathaniel.l.desim...@intel.com> Signed-off-by: Chasel Chiu <chasel.c...@intel.com> --- Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf | 3 +-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 17 ++++++++++++++++- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 25 +++++++++++++++++++------ 3 files changed, 36 insertions(+), 9 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf index 9218c8fe67..8bc2f8729f 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSm +++ m.inf @@ -1,7 +1,7 @@ ### @file # Component information file for the ThunderBolt Smm module. # -# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2018 - 2019, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -44,7 +44,6 @@ [Pcd] gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES [FixedPcd] gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 1dfe49a7ad..8dbdf25787 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -15,7 +15,6 @@ DEFINE PLATFORM_PACKAGE = MinPlatformPkg DEFINE PLATFORM_SI_PACKAGE = KabylakeSiliconPkg DEFINE PLATFORM_SI_BIN_PACKAGE = KabylakeSiliconBinPkg - DEFINE PLATFORM_FSP_BIN_PACKAGE = AmberLakeFspBinPkg DEFINE PLATFORM_BOARD_PACKAGE = KabylakeOpenBoardPkg DEFINE BOARD = KabylakeRvp3 DEFINE PROJECT = $(PLATFORM_BOARD_PACKAGE)/$(BOARD) @@ -40,6 +39,22 @@ DEFINE PLATFORM_FSP_BIN_PACKAGE = AmberLakeFspBinPkg !endif +[PcdsDynamicExDefault.common.DEFAULT] +!if gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == TRUE !if +gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 0 + # + # Include FSP DynamicEx PCD settings in Dispatch mode + # + !include $(PLATFORM_FSP_BIN_PACKAGE)/FspPcds.dsc + + # + # Override some FSP consumed PCD default value to match platform requirement. + # + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress +|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSp +aceGuid.PcdPciExpressRegionLength +!endif +!endif + ################################################################################ # # Defines Section - statements that will be processed to create a Makefile. diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc index 63d0c4c2e6..fbd43a6947 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d +++ sc @@ -48,7 +48,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 @@ -147,6 +147,15 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEBC000 gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE00000 + ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time. + # @Prompt Timeout for the BSP to detect all APs for the first time. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 + +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || +(gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1) + # + # In non-FSP build (EDK2 build) or FSP API mode below PCD are +FixedAtBuild + # (They will be DynamicEx in FSP Dispatch mode) + # ## Specifies max supported number of Logical Processors. # @Prompt Configure max supported number of Logical Processorss gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12 @@ -155,10 +164,6 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 # @Prompt Microcode Region size. gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0 - ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time. - # @Prompt Timeout for the BSP to detect all APs for the first time. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 - ## Specifies the AP wait loop state during POST phase. # The value is defined as below. # 1: Place AP in the Hlt-Loop state. @@ -167,6 +172,15 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 # @Prompt The AP wait loop state. gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 + +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGui +d.PcdPciExpressBaseAddress + +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSp +aceGuid.PcdPciExpressRegionLength +!else + # + # FSP Dispatch mode requires more platform memory as boot loader and +FSP sharing the same + # platform memory. + # + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000 +!endif # # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags @@ -294,4 +308,3 @@ gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax | 26 gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd | 100 gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax | 28 gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe| 0x00000001 - -- 2.19.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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