From a2480549c8eed0215f8f062bf1994472b1e75062 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Antoine=20C=C5=93ur?= Date: Thu, 11 Jul 2019 16:31:15 +0800 Subject: [PATCH] Revert "FmpDevicePkg: Fix various typos" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit f527942e6bdd9f198db90f2de99a0482e9be5b1b. Commit message was incorrect. Signed-off-by: Cœur --- .../FspSecCore/Ia32/FspApiEntryM.nasm | 4 +-- .../FspSecCore/Ia32/InitializeFpu.nasm | 4 +-- .../FspSecCore/Ia32/SaveRestoreSseNasm.inc | 4 +-- IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm | 4 +-- IntelFsp2Pkg/FspSecCore/SecFsp.c | 4 +-- IntelFsp2Pkg/FspSecCore/SecMain.c | 2 +- .../FspSecCore/Vtf0/Ia16/ResetVec.asm16 | 4 +-- IntelFsp2Pkg/Include/FspEas/FspApi.h | 8 ++--- .../Include/Library/FspSecPlatformLib.h | 4 +-- IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c | 12 +++---- .../BaseFspDebugLibSerialPort/DebugLib.c | 34 +++++++++---------- .../BaseFspSwitchStackLib/Ia32/Stack.nasm | 4 +-- .../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 4 +-- .../PlatformSecLibNull.c | 4 +-- IntelFsp2Pkg/Tools/GenCfgOpt.py | 2 +- IntelFsp2Pkg/Tools/PatchFv.py | 2 +- .../Tools/UserManuals/GenCfgOptUserManual.md | 2 +- .../Tools/UserManuals/PatchFvUserManual.md | 2 +- 18 files changed, 52 insertions(+), 52 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm index e7261b41cd..f14c18c7b9 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm @@ -194,9 +194,9 @@ StackSetupDone: ; ; Pass BFV into the PEI Core - ; It uses relative address to calculate the actual boot FV base + ; It uses relative address to calucate the actual boot FV base ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and - ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs, + ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs, ; they are different. The code below can handle both cases. ; call ASM_PFX(AsmGetFspBaseAddress) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm index ebc91c41e4..e1886ea11b 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2015, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -46,7 +46,7 @@ ASM_PFX(InitializeFloatingPointUnits): fldcw [ASM_PFX(mFpuControlWord)] ; - ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test + ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test ; whether the processor supports SSE instruction. ; mov eax, 1 diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index 4c321cbece..b257deb76c 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2015, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -150,7 +150,7 @@ NextAddress: fldcw [FpuControlWord] ; - ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test + ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test ; whether the processor supports SSE instruction. ; mov eax, 1 diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm index 5a7e27c240..d72212ed45 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2015, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -58,7 +58,7 @@ ASM_PFX(SecSwitchStack): mov esp, eax ; From now, esp is pointed to permanent memory ; - ; Fixup the ebp point to permanent memory + ; Fixup the ebp point to permenent memory ; mov eax, ebp sub eax, ebx diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c index 446d1730e9..6497c88ebe 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -169,7 +169,7 @@ FspGlobalDataInit ( SerialPortInitialize (); // - // Ensure the global data pointer is valid + // Ensure the golbal data pointer is valid // ASSERT (GetFspGlobalDataPointer () == PeiFspData); diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c b/IntelFsp2Pkg/FspSecCore/SecMain.c index a63d1336e4..cd3ab46ce2 100644 --- a/IntelFsp2Pkg/FspSecCore/SecMain.c +++ b/IntelFsp2Pkg/FspSecCore/SecMain.c @@ -110,7 +110,7 @@ SecStartup ( // |-------------------|----> // | | // | | - // | Heap | PeiTemporaryRamSize + // | Heap | PeiTemporayRamSize // | | // | | // |-------------------|----> TempRamBase diff --git a/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 b/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 index c519874809..f25de0206a 100644 --- a/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 +++ b/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 @@ -2,7 +2,7 @@ ; Reset Vector Data structure ; This structure is located at 0xFFFFFFC0 ; -; Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2014, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;; @@ -61,7 +61,7 @@ ApStartup: ; ; Jmp Rel16 instruction ; Use machine code directly in case of the assembler optimization - ; SEC entry point relative address will be fixed up by some build tool. + ; SEC entry point relatvie address will be fixed up by some build tool. ; ; Typically, SEC entry point is the function _ModuleEntryPoint() defined in ; SecEntry.asm diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/FspEas/FspApi.h index dcf489dbe6..1d38e639e6 100644 --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -2,7 +2,7 @@ Intel FSP API definition from Intel Firmware Support Package External Architecture Specification v2.0. - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -211,12 +211,12 @@ EFI_STATUS each FSP release. After FspMemInit completes its execution, it passes the pointer to the HobList and returns to the boot loader from where it was called. BootLoader is responsible to - migrate its stack and data to Memory. + migrate it's stack and data to Memory. FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the silicon initialization and provides bootloader an opportunity to get control after system memory is available and before the temporary RAM is torn down. - @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data structure. + @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data sructure. @param[out] HobListPtr Pointer to receive the address of the HOB list. @retval EFI_SUCCESS FSP execution environment was initialized successfully. @@ -271,7 +271,7 @@ EFI_STATUS @retval EFI_INVALID_PARAMETER Input parameters are invalid. @retval EFI_UNSUPPORTED The FSP calling conditions were not met. @retval EFI_DEVICE_ERROR FSP initialization failed. - @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3. + @retval FSP_STATUS_RESET_REQUIREDx A reset is reuired. These status codes will not be returned during S3. **/ typedef EFI_STATUS diff --git a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h index 4d01b5f6d9..48b04c5a90 100644 --- a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h +++ b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -66,7 +66,7 @@ SecCarInit ( ); /** - This function check the signature of UPD. + This function check the signture of UPD. @param[in] ApiIdx Internal index of the FSP API. @param[in] ApiParam Parameter of the FSP API. diff --git a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c index 17e895c345..927cee13d3 100644 --- a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c +++ b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -52,8 +52,8 @@ IsDefaultType ( @param[in] BaseAddress Base address. @param[in] Size Size. - @retval Zero Aligned. - @retval Non-Zero Not aligned. + @retval Zero Alligned. + @retval Non-Zero Not alligned. **/ UINT32 @@ -217,7 +217,7 @@ Power2MaxMemory ( } // - // Compute initial power of 2 size to return + // Compute inital power of 2 size to return // Result = GetPowerOfTwo64(MemoryLength); @@ -247,8 +247,8 @@ Power2MaxMemory ( @param[in] BaseAddress Base address. @param[in] Size Size. - @retval Zero Aligned. - @retval Non-Zero Not aligned. + @retval Zero Alligned. + @retval Non-Zero Not alligned. **/ UINT32 diff --git a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c index b34905365d..17688c7fcb 100644 --- a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c +++ b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c @@ -186,7 +186,7 @@ DebugBPrint ( } /** - Convert an UINT32 value into HEX string specified by Buffer. + Convert an UINT32 value into HEX string sepcified by Buffer. @param Value The HEX value to convert to string @param Buffer The pointer to the target buffer to be filled with HEX string @@ -211,8 +211,8 @@ FillHex ( Print a message of the form "ASSERT (): \n" to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of - PcdDebugPropertyMask is set then CpuBreakpoint() is called. Otherwise, if - DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugPropertyMask is set then + PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if + DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then CpuDeadLoop() is called. If neither of these bits are set, then this function returns immediately after the message is printed to the debug output device. DebugAssert() must actively prevent recursion. If DebugAssert() is called while @@ -265,8 +265,8 @@ DebugAssertInternal ( Print a message of the form "ASSERT (): \n" to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of - PcdDebugPropertyMask is set then CpuBreakpoint() is called. Otherwise, if - DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugPropertyMask is set then + PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if + DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then CpuDeadLoop() is called. If neither of these bits are set, then this function returns immediately after the message is printed to the debug output device. DebugAssert() must actively prevent recursion. If DebugAssert() is called while @@ -322,10 +322,10 @@ DebugClearMemory ( Returns TRUE if ASSERT() macros are enabled. This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of - PcdDebugPropertyMask is set. Otherwise FALSE is returned. + PcdDebugProperyMask is set. Otherwise FALSE is returned. - @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugPropertyMask is set. - @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugPropertyMask is clear. + @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set. + @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is clear. **/ BOOLEAN @@ -342,10 +342,10 @@ DebugAssertEnabled ( Returns TRUE if DEBUG() macros are enabled. This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of - PcdDebugPropertyMask is set. Otherwise FALSE is returned. + PcdDebugProperyMask is set. Otherwise FALSE is returned. - @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugPropertyMask is set. - @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugPropertyMask is clear. + @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is set. + @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is clear. **/ BOOLEAN @@ -361,10 +361,10 @@ DebugPrintEnabled ( Returns TRUE if DEBUG_CODE() macros are enabled. This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of - PcdDebugPropertyMask is set. Otherwise FALSE is returned. + PcdDebugProperyMask is set. Otherwise FALSE is returned. - @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugPropertyMask is set. - @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugPropertyMask is clear. + @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set. + @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is clear. **/ BOOLEAN @@ -381,10 +381,10 @@ DebugCodeEnabled ( Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled. This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of - PcdDebugPropertyMask is set. Otherwise FALSE is returned. + PcdDebugProperyMask is set. Otherwise FALSE is returned. - @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugPropertyMask is set. - @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugPropertyMask is clear. + @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set. + @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is clear. **/ BOOLEAN diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm index 6599901906..45cc974788 100644 --- a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm +++ b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm @@ -1,11 +1,11 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2016, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: ; -; Switch the stack from temporary memory to permanent memory. +; Switch the stack from temporary memory to permenent memory. ; ;------------------------------------------------------------------------------ diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm index aef7f96d1d..dc4af7c078 100644 --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm @@ -2,7 +2,7 @@ ; This is the code that goes from real-mode to protected mode. ; It consumes the reset vector, configures the stack. ; -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ;; @@ -54,7 +54,7 @@ ASM_PFX(SecPlatformInit): ; esp ; ; Description: -; Perform any essential early platform initialisation +; Perform any essential early platform initilaisation ; Setup a stack ; ;---------------------------------------------------------------------------- diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c index f7945b5240..50cb3142d2 100644 --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c @@ -1,7 +1,7 @@ /** @file Null instance of Platform Sec Lib. - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -10,7 +10,7 @@ #include /** - This function check the signature of UPD. + This function check the signture of UPD. @param[in] ApiIdx Internal index of the FSP API. @param[in] ApiParam Parameter of the FSP API. diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt.py index a42717caae..c4e1e6239d 100644 --- a/IntelFsp2Pkg/Tools/GenCfgOpt.py +++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py @@ -535,7 +535,7 @@ EndList Offset = 0 else: if DscLine.startswith('!'): - print("ERROR: Unrecognized directive for line '%s'" % DscLine) + print("ERROR: Unrecoginized directive for line '%s'" % DscLine) raise SystemExit if not Handle: continue diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py index edb30c816b..2173984dea 100644 --- a/IntelFsp2Pkg/Tools/PatchFv.py +++ b/IntelFsp2Pkg/Tools/PatchFv.py @@ -160,7 +160,7 @@ class Symbols: # def createDicts (self, fvDir, fvNames): # - # If the fvDir is not a directory, then raise an exception + # If the fvDir is not a dirctory, then raise an exception # if not os.path.isdir(fvDir): raise Exception ("'%s' is not a valid directory!" % FvDir) diff --git a/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md b/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md index 0a0f592801..938c18416d 100644 --- a/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md +++ b/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md @@ -213,7 +213,7 @@ in the third. ```@Bsf NAME:{Variable 1} TYPE:{Combo}``` There is a special **None** type that puts the variable in the **StructDef** -region of the BSF, but doesn't put it in any **Page** section. This makes the +region of the BSF, but doesn?t put it in any **Page** section. This makes the variable visible to BCT, but not to the end user. ###HELP diff --git a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md index 5f1031e729..becaf96b21 100644 --- a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md +++ b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md @@ -30,7 +30,7 @@ FSP tree. The example used contains Windows batch script %VARIABLES%. -#FvFileBaseNames (Argument 2: Optional Part 1) +#FvFileBaseNames (Argument 2: 0ptional Part 1) The firmware volume file base names (**_FvFileBaseNames_**) are the independent Fv?s that are to be patched within the FD. (0 or more in the form **FVFILEBASENAME:**) The colon **:** is used for delimiting the single -- 2.20.1 (Apple Git-117)