Reviewed-by: Eric Dong <eric.d...@intel.com> > -----Original Message----- > From: Ni, Ray > Sent: Thursday, August 1, 2019 5:58 PM > To: devel@edk2.groups.io > Cc: Dong, Eric <eric.d...@intel.com>; Laszlo Ersek <ler...@redhat.com> > Subject: [PATCH v4 1/8] UefiCpuPkg/MpInitLib: Enable 5-level paging for AP > when BSP's enabled > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008 > > MpInitLib is the library that's responsible to wake up APs to provide MP PPI > and Protocol services. > > The patch synchronizes BSP's CR4.LA57 to each AP's CR4.LA57. > Without this change, AP may enter to GP fault when BSP's 5-level page table > is set to AP during AP wakes up. > > Signed-off-by: Ray Ni <ray...@intel.com> > Cc: Eric Dong <eric.d...@intel.com> > Cc: Laszlo Ersek <ler...@redhat.com> > --- > UefiCpuPkg/Library/MpInitLib/MpLib.c | 13 +++++++++++++ > UefiCpuPkg/Library/MpInitLib/MpLib.h | 4 ++++ > UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc | 3 ++- > UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 14 +++++++++++++- > 4 files changed, 32 insertions(+), 2 deletions(-) > > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c > b/UefiCpuPkg/Library/MpInitLib/MpLib.c > index 572495ec36..d2f18027cd 100644 > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c > @@ -790,6 +790,7 @@ FillExchangeInfoData ( > volatile MP_CPU_EXCHANGE_INFO *ExchangeInfo; > UINTN Size; > IA32_SEGMENT_DESCRIPTOR *Selector; > + IA32_CR4 Cr4; > > ExchangeInfo = CpuMpData->MpCpuExchangeInfo; > ExchangeInfo->Lock = 0; > @@ -814,6 +815,18 @@ FillExchangeInfoData ( > > ExchangeInfo->InitializeFloatingPointUnitsAddress = > (UINTN)InitializeFloatingPointUnits; > > + // > + // We can check either CPUID(7).ECX[bit16] or check CR4.LA57[bit12] > + // to determin whether 5-Level Paging is enabled. > + // CPUID(7).ECX[bit16] shows CPU's capability, CR4.LA57[bit12] shows > + // current system setting. > + // Using latter way is simpler because it also eliminates the needs > + to // check whether platform wants to enable it. > + // > + Cr4.UintN = AsmReadCr4 (); > + ExchangeInfo->Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); > + DEBUG ((DEBUG_INFO, "%a: 5-Level Paging = %d\n", gEfiCallerBaseName, > + ExchangeInfo->Enable5LevelPaging)); > + > // > // Get the BSP's data of GDT and IDT > // > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h > b/UefiCpuPkg/Library/MpInitLib/MpLib.h > index effa235778..4b12f91d47 100644 > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h > @@ -185,6 +185,10 @@ typedef struct { > UINT16 ModeTransitionSegment; > UINT32 ModeHighMemory; > UINT16 ModeHighSegment; > + // > + // Enable5LevelPaging indicates whether 5-level paging is enabled in long > mode. > + // > + BOOLEAN Enable5LevelPaging; > } MP_CPU_EXCHANGE_INFO; > > #pragma pack() > diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc > b/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc > index 467f54a860..58ef369342 100644 > --- a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc > +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc > @@ -1,5 +1,5 @@ > > ;------------------------------------------------------------------------------ > ; -; > Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR> > +; Copyright (c) 2015 - 2019, Intel Corporation. All rights > +reserved.<BR> > ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: > @@ -40,3 +40,4 @@ ModeTransitionMemoryLocation equ LockLocation > + 94h > ModeTransitionSegmentLocation equ LockLocation + 98h > ModeHighMemoryLocation equ LockLocation + 9Ah > ModeHighSegmentLocation equ LockLocation + 9Eh > +Enable5LevelPagingLocation equ LockLocation + 0A0h > diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm > b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm > index cea90f3d4d..87f2523e85 100644 > --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm > +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm > @@ -1,5 +1,5 @@ > > ;------------------------------------------------------------------------------ > ; -; > Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR> > +; Copyright (c) 2015 - 2019, Intel Corporation. All rights > +reserved.<BR> > ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: > @@ -100,6 +100,18 @@ SkipEnableExecuteDisableBit: > ; > mov eax, cr4 > bts eax, 5 > + > + mov esi, Enable5LevelPagingLocation > + cmp byte [ebx + esi], 0 > + jz SkipEnable5LevelPaging > + > + ; > + ; Enable 5 Level Paging > + ; > + bts eax, 12 ; Set LA57=1. > + > +SkipEnable5LevelPaging: > + > mov cr4, eax > > ; > -- > 2.21.0.windows.1
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