Thank you for the patch! I reviewed the code and noticed select issues 
explained below.

1. The following construction:

if (RegEbx == 0) {
DEBUG ((DEBUG_ERROR, "The CPU is not capble for Core Crystal Clock Frequency 
ASSERT (RegEbx != 0);

Does not look good to me, and in my opinion, should be written differently:

if (RegEbx == 0 || RegEax == 0 ) {
DEBUG ((DEBUG_ERROR, "The CPU is not capble for Core Crystal Clock Frequency 
ASSERT (RegEbx != 0);
ASSERT (RegEax != 0);
return 0;

The reason for the above code being wrong is potential division by zero below, 
which behaviour is undefined (and in fact unknown due to unspecified interrupt 
table state). Even though the intent is to not permit the use of this library 
on an unsupported platform, runtime checks and assertions are essentially 
NO-OPs, should be separate and not confused. For this to work properly the call 
to CpuidCoreClockCalculateTscFrequency should happen in library constructor 
with EFI_UNSUPPORTED return on CpuidCoreClockCalculateTscFrequency returning 0.

2. The notes about crystal clock frequency for 06_55H CPU signature:
"25000000 - Intel Xeon Processor Scalable Family with CPUID signature 
# Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 

are misleading in both this library and Intel SDM. Intel Xeon W processors have 
the same CPUID signature ( 06_55H) , they report 0 crystal clock frequency, and 
their crystal clock frequency is 24 MHz. This should at least be mentioned in 
the lower part mentioning Intel Xeon W Processor Family(24MHz).

Actually, given that many Intel guys are here, I wonder whether anybody knows 
if there is any better approach to distinguish Xeon Scalable CPUs and Xeon W 
CPUs besides using brand string or using marketing frequency from CPUID 16H to 
determine crystal clock frequency (this is what Linux does at the moment)?

3. Intel Atom Denverton with CPUID signature (06_5FH), also known as Goldmont 
X, reports 0 crystal clock frequency as well, and has 25 MHz frequency. This is 
missing from SDM, but once again I believe it should be included in the two 
places from the above to avoid confusion.

Besides these 3 points, honestly, the library itself appears to be very limited 
for anything but embedding it into the firmware with known hardware, which 
already works just fine by defining the PCD. Missing 0 crystal clock frequency 
handling in runtime with hardcoding the PCD value looks very bad, because the 
number of modern Intel CPU models reporting 0 crystal clock frequency and 
having non 24 MHz frequency is quite far from 0. This makes the library 
essentially impossible to use in any UEFI application or third-party product 
even when targeting Skylake+ generation. To resolute this I vote for additional 
detection functionality to be added to the library to obtain crystal clock 
frequency when the CPUID reports 0. The PCD could be the last resort when no 
other method works. My opinion is that this should be resolved prior to merging 
the patch.

Best regards,

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