Reviewed-by: Nate DeSimone <nathaniel.l.desim...@intel.com> -----Original Message----- From: Kubacki, Michael A Sent: Friday, August 16, 2019 5:16 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V <rangasai.v.chaga...@intel.com>; Chiu, Chasel <chasel.c...@intel.com>; Desimone, Nathaniel L <nathaniel.l.desim...@intel.com>; Gao, Liming <liming....@intel.com>; Kinney, Michael D <michael.d.kin...@intel.com>; Sinha, Ankit <ankit.si...@intel.com> Subject: [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add Private/Protocol include headers
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082 Adds the following header files: * Pch/Include/Private/Protocol Cc: Sai Chaganty <rangasai.v.chaga...@intel.com> Cc: Chasel Chiu <chasel.c...@intel.com> Cc: Nate DeSimone <nathaniel.l.desim...@intel.com> Cc: Liming Gao <liming....@intel.com> Cc: Michael D Kinney <michael.d.kin...@intel.com> Cc: Ankit Sinha <ankit.si...@intel.com> Signed-off-by: Michael Kubacki <michael.a.kuba...@intel.com> --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsArea.h | 31 ++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoTrap.h | 37 ++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsArea.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsArea.h new file mode 100644 index 0000000000..75003c82ad --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/Pc +++ hNvsArea.h @@ -0,0 +1,31 @@ +/** @file + This file defines the PCH NVS Area Protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PCH_NVS_AREA_H_ +#define _PCH_NVS_AREA_H_ + +// +// PCH NVS Area definition +// +#include <Private/PchNvsAreaDef.h> + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchNvsAreaProtocolGuid; + +/** + This protocol is used to sync PCH information from POST to runtime ASL. + This protocol exposes the pointer of PCH NVS Area only. Please refer +to + ASL definition for PCH NVS AREA. +**/ +typedef struct { + PCH_NVS_AREA *Area; +} PCH_NVS_AREA_PROTOCOL; + +#endif // _PCH_NVS_AREA_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoTrap.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoTrap.h new file mode 100644 index 0000000000..2cd6b85d29 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/Pc +++ ieIoTrap.h @@ -0,0 +1,37 @@ +/** @file + This file defines the PCH PCIE IoTrap Protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PCH_PCIE_IOTRAP_H_ +#define _PCH_PCIE_IOTRAP_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchPcieIoTrapProtocolGuid; + +// +// Forward reference for ANSI C compatibility // typedef struct +_PCH_PCIE_IOTRAP_PROTOCOL PCH_PCIE_IOTRAP_PROTOCOL; + +/// +/// Pcie Trap valid types +/// +typedef enum { + PciePmTrap, + PcieTrapTypeMaximum +} PCH_PCIE_TRAP_TYPE; + +/** + This protocol is used to provide the IoTrap address to trigger PCH +PCIE call back events **/ struct _PCH_PCIE_IOTRAP_PROTOCOL { + UINT16 PcieTrapAddress; +}; + +#endif -- 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45925): https://edk2.groups.io/g/devel/message/45925 Mute This Topic: https://groups.io/mt/32918179/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
