PeiCoreInfoHobLib - This is the library to create RISC-V core characteristics for building up RISC-V related SMBIOS records to support the unified boot loader and OS image.
- RiscVPlatformTimerLib This is U500 platform timer library which has the platform-specific timer implementation. - SerialPortLib U500 serial port platform library Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gilbert Chen <gilbert.c...@hpe.com> --- .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 201 +++++++++++++++++ .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 64 ++++++ .../RiscVPlatformTimerLib.inf | 46 ++++ .../RiscVPlatformTimerLib/RiscVPlatformTimerLib.s | 54 +++++ .../U500Pkg/Library/SerialIoLib/SerialIoLib.inf | 37 +++ .../U500Pkg/Library/SerialIoLib/SerialPortLib.c | 247 +++++++++++++++++++++ .../Library/SerialIoLib/U500SerialPortLib.uni | 22 ++ 7 files changed, 671 insertions(+) create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.s create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPortLib.uni diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c new file mode 100644 index 0000000..2db4fdc --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -0,0 +1,201 @@ +/**@file + Build up platform processor information. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// The package level header files this module uses +// +#include <PiPei.h> + +// +// The Library classes this module consumes +// +#include <Library/DebugLib.h> +#include <Library/HobLib.h> +#include <Library/BaseMemoryLib.h> + +#include <SmbiosProcessorSpecificData.h> +#include <ProcessorSpecificDataHob.h> +#include <SiFiveU5MCCoreplex.h> +#include <Library/SiFiveE51.h> +#include <Library/SiFiveU54.h> + +/** + Build up processor-specific HOB for U5MC Coreplex + + @param UniqueId Unique ID of this U5MC Coreplex processor + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU5MCCoreplexProcessorSpecificDataHob ( + IN UINTN UniqueId + ) +{ + EFI_STATUS Status; + UINT32 HartIdNumber; + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *GuidHobData; + EFI_GUID *ParentCoreGuid; + BOOLEAN MCSupport; + + DEBUG ((EFI_D_INFO, "Building U5 Coreplex processor information HOB\n")); + + HartIdNumber = 0; + ParentCoreGuid = PcdGetPtr(PcdSiFiveU5MCCoreplexGuid); + MCSupport = PcdGetBool (PcdE5MCSupported); + if (MCSupport == TRUE) { + Status = CreateE51CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, HartIdNumber, FALSE, &GuidHobData); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Faile to build U5MC processor informatino HOB\n")); + ASSERT (FALSE); + } + HartIdNumber ++; + DEBUG ((EFI_D_INFO, "Support E5 Monitor core on U500 platform, HOB at address 0x%x\n", GuidHobData)); + } + for (; HartIdNumber < (FixedPcdGet32 (PcdNumberofU5Cores) + (UINT32)MCSupport); HartIdNumber ++) { + Status = CreateU54CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, HartIdNumber, (HartIdNumber == FixedPcdGet32 (PcdBootHartId))? TRUE: FALSE, &GuidHobData); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Faile to build U5MC processor informatino HOB\n")); + ASSERT (FALSE); + } + DEBUG ((EFI_D_INFO, "Support U5 application core on U500 platform, HOB Data at address 0x%x\n", GuidHobData)); + } + DEBUG ((EFI_D_INFO, "Support %d U5 application cores on U500 platform\n", HartIdNumber - (UINT32)MCSupport)); + + if (HartIdNumber != FixedPcdGet32 (PcdHartCount)) { + DEBUG ((EFI_D_ERROR, "Improper core settings...\n")); + DEBUG ((EFI_D_ERROR, " PcdHartCount\n")); + DEBUG ((EFI_D_ERROR, " PcdNumberofU5Cores\n")); + DEBUG ((EFI_D_ERROR, " PcdE5MCSupported\n\n")); + ASSERT (FALSE); + } + return Status; +} + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns this core. + @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_HOB. The pointers + maintained in this structure is only valid before memory is discovered. + Access to those pointers after memory is installed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU5MCProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr + ) +{ + EFI_GUID *GuidPtr; + RISC_V_PROCESSOR_TYPE4_DATA_HOB ProcessorDataHob; + RISC_V_PROCESSOR_TYPE7_DATA_HOB L2CacheDataHob; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB SmbiosDataHob; + RISC_V_PROCESSOR_TYPE4_DATA_HOB *ProcessorDataHobPtr; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2CacheDataHobPtr; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB *SmbiosDataHobPtr; + + DEBUG ((EFI_D_INFO, "%a: Entry\n", __FUNCTION__)); + + if (SmbiosHobPtr == NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Build up SMBIOS type 7 L2 cache record. + // + ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB)); + L2CacheDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid)); + L2CacheDataHob.ProcessorUid = ProcessorUid; + L2CacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 | \ + RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \ + RISC_V_CACHE_CONFIGURATION_ENABLED | \ + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; + L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1; + L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1; + L2CacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeUnified; + L2CacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR; + GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); + L2CacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDataHob (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB)); + if (L2CacheDataHobPtr == NULL) { + DEBUG ((EFI_D_ERROR, "Fail to create GUID HOB of SiFive U5 MC Coreplex L2 cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n")); + ASSERT (FALSE); + } + + // + // Build up SMBIOS type 4 record. + // + ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DATA_HOB)); + ProcessorDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid)); + ProcessorDataHob.ProcessorUid = ProcessorUid; + ProcessorDataHob.SmbiosType4Processor.Socket = TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.ProcessorType = CentralProcessor; + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily = ProcessorFamilyIndicatorFamily2; + ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture = TO_BE_FILLED_BY_VENDOR; + SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, sizeof (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE); + ProcessorDataHob.SmbiosType4Processor.ProcessorVersion = TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability3_3V = 1; + ProcessorDataHob.SmbiosType4Processor.ExternalClock = TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.MaxSpeed = TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.CurrentSpeed = TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.Status = TO_BE_FILLED_BY_CODE; + ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade = TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.L1CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L2CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L3CacheHandle = 0xffff; + ProcessorDataHob.SmbiosType4Processor.SerialNumber = TO_BE_FILLED_BY_CODE; + ProcessorDataHob.SmbiosType4Processor.AssetTag = TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.PartNumber = TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.CoreCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported); + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported); + ProcessorDataHob.SmbiosType4Processor.ThreadCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported); + ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics = (UINT16)(1 << 2); // 64-bit capable + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 = ProcessorFamilyRiscVRV64; + ProcessorDataHob.SmbiosType4Processor.CoreCount2 = 0; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 = 0; + ProcessorDataHob.SmbiosType4Processor.ThreadCount2 = 0; + GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid); + ProcessorDataHobPtr = (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)BuildGuidDataHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DATA_HOB)); + if (ProcessorDataHobPtr == NULL) { + DEBUG ((EFI_D_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex RISC_V_PROCESSOR_TYPE4_DATA_HOB.\n")); + ASSERT (FALSE); + } + + ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HOB)); + SmbiosDataHob.Processor = ProcessorDataHobPtr; + SmbiosDataHob.L1InstCache = NULL; + SmbiosDataHob.L1DataCache = NULL; + SmbiosDataHob.L2Cache = L2CacheDataHobPtr; + SmbiosDataHob.L3Cache = NULL; + GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid); + SmbiosDataHobPtr = (RISC_V_PROCESSOR_SMBIOS_DATA_HOB *)BuildGuidDataHob (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HOB)); + if (SmbiosDataHobPtr == NULL) { + DEBUG ((EFI_D_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex RISC_V_PROCESSOR_SMBIOS_DATA_HOB.\n")); + ASSERT (FALSE); + } + *SmbiosHobPtr = SmbiosDataHobPtr; + DEBUG ((EFI_D_INFO, "%a: Exit\n", __FUNCTION__)); + return EFI_SUCCESS; +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf new file mode 100644 index 0000000..716d0bb --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf @@ -0,0 +1,64 @@ +## @file +# Library instance to create core information HOB +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SiliconSiFiveU5MCCoreplexInfoLib + FILE_GUID = 4E397A71-5164-4E69-9884-70CBE2740AAB + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconSiFiveU5MCCoreplexInfoLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = RISCV +# + +[Sources] + CoreInfoHob.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/RiscV/RiscVPlatformPkg.dec + Platform/RiscV/SiFive/U500Pkg/U500.dec + Silicon/SiFive/SiFive.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + MemoryAllocationLib + PrintLib + SiliconSiFiveE51CoreInfoLib + SiliconSiFiveU54CoreInfoLib + +[Guids] + gUefiRiscVPlatformU500PkgTokenSpaceGuid + +[Ppis] + +[FixedPcd] + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU54CoreGuid + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveE51CoreGuid + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU5MCCoreplexGuid + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdNumberofU5Cores + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdE5MCSupported + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf b/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf new file mode 100644 index 0000000..d1553da --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf @@ -0,0 +1,46 @@ +## @file +# RISC-V CPU lib to override timer mechanism for U500 platform. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> +# Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = RiscVPlatformTimerLib + FILE_GUID = AFA75BBD-DE9D-4E77-BD88-1EA401BE931D + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RiscVPlatformTimerLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = RISCV32 RISCV64 +# + +[Sources] + +[Sources.RISCV32] + RiscVPlatformTimerLib.s + +[Sources.RISCV64] + RiscVPlatformTimerLib.s + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + Platform/RiscV/SiFive/U500Pkg/U500.dec + + diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.s b/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.s new file mode 100644 index 0000000..fd22466 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.s @@ -0,0 +1,54 @@ +//------------------------------------------------------------------------------ +// +// SiFive U500 Timer CSR functions. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +//------------------------------------------------------------------------------ +#include <Base.h> +#include <RiscV.h> +#include <U500Clint.h> + +.data + +.text +.align 3 + +.global ASM_PFX(RiscVReadMachineTimer) +.global ASM_PFX(RiscVSetMachineTimerCmp) +.global ASM_PFX(RiscVReadMachineTimerCmp) + +// +// Read machine timer CSR. +// @retval a0 : 64-bit machine timer. +// +ASM_PFX (RiscVReadMachineTimer): + li t1, CLINT_REG_MTIME + ld a0, (t1) + ret + +// +// Set machine timer compare CSR. +// @param a0 : UINT64 +// +ASM_PFX (RiscVSetMachineTimerCmp): + li t1, CLINT_REG_MTIMECMP0 + sd a0, (t1) + ret + +// +// Read machine timer compare CSR. +// @param a0 : UINT64 +// +ASM_PFX (RiscVReadMachineTimerCmp): + li t1, CLINT_REG_MTIMECMP0 + ld a0, (t1) + ret diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf new file mode 100644 index 0000000..6245484 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf @@ -0,0 +1,37 @@ +## @file +# Library instance for SerialIo library class +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> +# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = U500SerialPortLib + MODULE_UNI_FILE = U500SerialPortLib.uni + FILE_GUID = FCC4FD2B-2FF6-4FFA-B363-7C1111E5DCE9 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SerialPortLib + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + Platform/RiscV/RiscVPlatformPkg.dec + +[LibraryClasses] + BaseLib + IoLib + RiscVOpensbiLib + +[Sources] + SerialPortLib.c + diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c new file mode 100644 index 0000000..84475fe --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c @@ -0,0 +1,247 @@ +/** @file + UART Serial Port library functions + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Library/IoLib.h> +#include <Library/SerialPortLib.h> +#include <sbi_utils/serial/sifive-uart.h> + +#define REG32(p, i) ((p)[(i) >> 2]) + +//--------------------------------------------- +// UART Register Offsets +//--------------------------------------------- + +#define UART_REG_IP 0x14 + #define UART_IP_RXWM 0x02 + +//--------------------------------------------- +// UART Settings +//--------------------------------------------- + +#define U500_UART_ADDR 0x54000000 +#define U500_UART_BAUDRATE 115200 +#define U500_SYS_CLK 100000000 + +/** + Initialize the serial device hardware. + + If no initialization is required, then return RETURN_SUCCESS. + If the serial device was successfuly initialized, then return RETURN_SUCCESS. + If the serial device could not be initialized, then return RETURN_DEVICE_ERROR. + + @retval RETURN_SUCCESS The serial device was initialized. + @retval RETURN_DEVICE_ERROR The serail device could not be initialized. + +**/ +RETURN_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + if (sifive_uart_init (U500_UART_ADDR, U500_SYS_CLK/2, U500_UART_BAUDRATE) != 0) { + return EFI_DEVICE_ERROR; + } + return RETURN_SUCCESS; +} + +/** + Write data from buffer to serial device. + + Writes NumberOfBytes data bytes from Buffer to the serial device. + The number of bytes actually written to the serial device is returned. + If the return value is less than NumberOfBytes, then the write operation failed. + + If Buffer is NULL, then ASSERT(). + + If NumberOfBytes is zero, then return 0. + + @param Buffer Pointer to the data buffer to be written. + @param NumberOfBytes Number of bytes to written to the serial device. + + @retval 0 NumberOfBytes is 0. + @retval >0 The number of bytes written to the serial device. + If this value is less than NumberOfBytes, then the write operation failed. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + UINTN i; + + if (Buffer == NULL) { + return 0; + } + + for(i=0; i < NumberOfBytes; i++) { + sifive_uart_putc (Buffer[i]); + } + + return i; +} + + +/** + Reads data from a serial device into a buffer. + + @param Buffer Pointer to the data buffer to store the data read from the serial device. + @param NumberOfBytes Number of bytes to read from the serial device. + + @retval 0 NumberOfBytes is 0. + @retval >0 The number of bytes read from the serial device. + If this value is less than NumberOfBytes, then the read operation failed. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + UINTN i; + + if (NULL == Buffer) { + return 0; + } + + for(i=0; i < NumberOfBytes; i++) { + Buffer[i] = (UINT8)sifive_uart_getc (); + } + + return i; +} + +/** + Polls a serial device to see if there is any data waiting to be read. + + Polls aserial device to see if there is any data waiting to be read. + If there is data waiting to be read from the serial device, then TRUE is returned. + If there is no data waiting to be read from the serial device, then FALSE is returned. + + @retval TRUE Data is waiting to be read from the serial device. + @retval FALSE There is no data waiting to be read from the serial device. + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + static volatile UINT32 * const uart = (void *)(U500_UART_ADDR); + UINT32 ip; + + ip = REG32(uart, UART_REG_IP); + if(ip & UART_IP_RXWM) { + return TRUE; + } + else { + return FALSE; + } +} + +/** + Sets the control bits on a serial device. + + @param Control Sets the bits of Control that are settable. + + @retval RETURN_SUCCESS The new control bits were set on the serial device. + @retval RETURN_UNSUPPORTED The serial device does not support this operation. + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetControl ( + IN UINT32 Control + ) +{ + + return RETURN_SUCCESS; +} + +/** + Retrieve the status of the control bits on a serial device. + + @param Control A pointer to return the current control signals from the serial device. + + @retval RETURN_SUCCESS The control bits were read from the serial device. + @retval RETURN_UNSUPPORTED The serial device does not support this operation. + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortGetControl ( + OUT UINT32 *Control + ) +{ + *Control = 0; + return RETURN_SUCCESS; +} + +/** + Sets the baud rate, receive FIFO depth, transmit/receice time out, parity, + data bits, and stop bits on a serial device. + + @param BaudRate The requested baud rate. A BaudRate value of 0 will use the + device's default interface speed. + On output, the value actually set. + @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the + serial interface. A ReceiveFifoDepth value of 0 will use + the device's default FIFO depth. + On output, the value actually set. + @param Timeout The requested time out for a single character in microseconds. + This timeout applies to both the transmit and receive side of the + interface. A Timeout value of 0 will use the device's default time + out value. + On output, the value actually set. + @param Parity The type of parity to use on this serial device. A Parity value of + DefaultParity will use the device's default parity value. + On output, the value actually set. + @param DataBits The number of data bits to use on the serial device. A DataBits + vaule of 0 will use the device's default data bit setting. + On output, the value actually set. + @param StopBits The number of stop bits to use on this serial device. A StopBits + value of DefaultStopBits will use the device's default number of + stop bits. + On output, the value actually set. + + @retval RETURN_SUCCESS The new attributes were set on the serial device. + @retval RETURN_UNSUPPORTED The serial device does not support this operation. + @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value. + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetAttributes ( + IN OUT UINT64 *BaudRate, + IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ) +{ + return RETURN_SUCCESS; +} + diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPortLib.uni b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPortLib.uni new file mode 100644 index 0000000..a1ad72e --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPortLib.uni @@ -0,0 +1,22 @@ +// /** @file +// Library instance for SerialIo library class +// +// Library instance for SerialIO library class. +// +// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Library instance for SerialIO library class" + +#string STR_MODULE_DESCRIPTION #language en-US "Library instance for SerialIO library class." + -- 2.7.4 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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