This patch can also be viewed in the following repo:- https://github.com/ashrafj/edk2-staging/commit/91e85bdb96600e72d5d7ab4d170089abcf1fe4fb
Thanks Ashraf > -----Original Message----- > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Javeed, > Ashraf > Sent: Saturday, February 8, 2020 1:35 AM > To: devel@edk2.groups.io > Cc: Wang, Jian J <jian.j.w...@intel.com>; Wu, Hao A <hao.a...@intel.com>; > Ni, Ray <ray...@intel.com> > Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 04/12] > PciBusDxe: New PCI Express feature Max_Read_Req_Size > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2194 > > The code changes are made to enable the configuration of PCI Express feature > Max_Read_Req_Size (MRRS), which defines the memory read request size for > the PCI transactions, as per the PCI Base Specification 4 Revision 1. > > The code changes are made to configure a common value that is applicable to > all the child nodes originating from the root bridge device instance, based on > following 3 criteria:- > (1) if platform defines MRRS device policy for any one PCI device in the > tree than align all the devices in the PCI tree to that same value > (2) if platform does not provide device policy for any of the devices in > the PCI tree than setup the MRRS value equivalent to MPS value for > all PCI devices to meet the criteria for the isochronous traffic > (3) if platform does not provide device policy for any of the devices and > it has not selected the MPS to be configured either; than the config- > uration of the MRRS is performed based on highest common value of the > MPS advertized in the PCI device capability registers of the devices > > This programming of MRRS gets the device-specific platform policy using the > new PCI Express Platform Protocol interface, defined in the below feature > request:- https://bugzilla.tianocore.org/show_bug.cgi?id=1954 > > Signed-off-by: Ashraf Javeed <ashraf.jav...@intel.com> > Cc: Jian J Wang <jian.j.w...@intel.com> > Cc: Hao A Wu <hao.a...@intel.com> > Cc: Ray Ni <ray...@intel.com> > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 1 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c | 190 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h | 45 > +++++++++++++++++++++++++++++++++++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 20 > +++++++++++++++++++- > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 9 +++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 81 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h | 15 > +++++++++++++++ > 7 files changed, 360 insertions(+), 1 deletion(-) > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > index 5dc5f61..77b44c0 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > @@ -288,6 +288,7 @@ struct _PCI_IO_DEVICE { > // > UINT16 BridgeIoAlignment; > UINT8 SetupMPS; > + UINT8 SetupMRRS; > }; > > #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ diff --git > a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c > index 6084446..2810158 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c > @@ -191,3 +191,193 @@ ProgramMaxPayloadSize ( > return Status; > } > > +EFI_STATUS > +ConditionalCasMaxReadReqSize ( > + IN PCI_IO_DEVICE *PciDevice, > + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE > +*PciExpressConfigurationTable > + ) > +{ > + // > + // align the Max_Read_Request_Size of the PCI tree based on 3 conditions: > + // first, if user defines MRRS for any one PCI device in the tree > +than align > + // all the devices in the PCI tree. > + // second, if user override is not define for this PCI tree than > +setup the MRRS > + // based on MPS value of the tree to meet the criteria for the > +isochronous > + // traffic. > + // third, if no user override, or platform firmware policy has not > +selected > + // this PCI bus driver to configure the MPS; than configure the MRRS > +to a > + // highest common value of PCI device capability for the MPS found > +among all > + // the PCI devices in this tree > + // > + if (PciExpressConfigurationTable) { > + if (PciExpressConfigurationTable->Lock_Max_Read_Request_Size) { > + PciDevice->SetupMRRS = PciExpressConfigurationTable- > >Max_Read_Request_Size; > + } else { > + if (mPciExpressPlatformPolicy.Mps) { > + PciDevice->SetupMRRS = PciDevice->SetupMPS; > + } else { > + PciDevice->SetupMRRS = MIN ( > + PciDevice->SetupMRRS, > + > PciExpressConfigurationTable->Max_Read_Request_Size > + ); > + } > + PciExpressConfigurationTable->Max_Read_Request_Size = PciDevice- > >SetupMRRS; > + } > + } > + DEBUG (( DEBUG_INFO, "MRRS: %d,", PciDevice->SetupMRRS)); > + > + return EFI_SUCCESS; > +} > + > +/** > + The main routine which process the PCI feature Max_Read_Req_Size as > +per the > + device-specific platform policy, as well as in complaince with the > +PCI Base > + specification Revision 4, that aligns the value for the entire PCI > +heirarchy > + starting from its physical PCI Root port / Bridge device. > + > + @param PciDevice A pointer to the PCI_IO_DEVICE. > + @param PciExpressConfigurationTable pointer to > + PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE > + > + @retval EFI_SUCCESS processing of PCI feature > Max_Read_Req_Size > + is successful. > +**/ > +EFI_STATUS > +SetupMaxReadReqSize ( > + IN PCI_IO_DEVICE *PciDevice, > + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE > +*PciExpressConfigurationTable > + ) > +{ > + PCI_REG_PCIE_DEVICE_CAPABILITY PciDeviceCap; > + UINT8 MrrsValue; > + > + PciDeviceCap.Uint32 = > + PciDevice->PciExpressCapabilityStructure.DeviceCapability.Uint32; > + > + if (PciDevice->SetupMRRS == EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_AUTO) > { > + // > + // The maximum read request size is not the data packet size of the TLP, > + // but the memory read request size, and set to the function as a > requestor > + // to not exceed this limit. > + // However, for the PCI device capable of isochronous traffic; this > memory > read > + // request size should not extend beyond the Max_Payload_Size. Thus, in > case if > + // device policy return by platform indicates to set as per device > capability > + // than set as per Max_Payload_Size configuration value > + // > + if (mPciExpressPlatformPolicy.Mps) { > + MrrsValue = PciDevice->SetupMPS; > + } else { > + // > + // in case this driver is not required to configure the > Max_Payload_Size > + // than consider programming HCF of the device capability's > Max_Payload_Size > + // in this PCI hierarchy; thus making this an implementation specific > feature > + // which the platform should avoid. For better results, the platform > should > + // make both the Max_Payload_Size & Max_Read_Request_Size to be > configured > + // by this driver > + // > + MrrsValue = (UINT8)PciDeviceCap.Bits.MaxPayloadSize; > + } > + } else { > + // > + // override as per platform based device policy > + // > + MrrsValue = SetDevicePolicyPciExpressMrrs (PciDevice->SetupMRRS); > + // > + // align this device's Max_Read_Request_Size value to the entire PCI tree > + // > + if (PciExpressConfigurationTable) { > + if (!PciExpressConfigurationTable->Lock_Max_Read_Request_Size) { > + PciExpressConfigurationTable->Lock_Max_Read_Request_Size = TRUE; > + PciExpressConfigurationTable->Max_Read_Request_Size = MrrsValue; > + } else { > + // > + // in case of another user enforced value of MRRS within the same > tree, > + // pick the smallest between the locked value and this value; to set > + // across entire PCI tree nodes > + // > + MrrsValue = MIN ( > + MrrsValue, > + PciExpressConfigurationTable->Max_Read_Request_Size > + ); > + PciExpressConfigurationTable->Max_Read_Request_Size = MrrsValue; > + } > + } > + } > + // > + // align this device's Max_Read_Request_Size to derived configuration > + value // PciDevice->SetupMRRS = MrrsValue; > + > + return ConditionalCasMaxReadReqSize ( > + PciDevice, > + PciExpressConfigurationTable > + ); > +} > + > + > +/** > + Overrides the PCI Device Control register Max_Read_Req_Size register > +field; if > + the hardware value is different than the intended value. > + > + @param PciDevice A pointer to the PCI_IO_DEVICE instance. > + > + @retval EFI_SUCCESS The data was read from or written to the PCI > controller. > + @retval EFI_UNSUPPORTED The address range specified by Offset, Width, > and Count is not > + valid for the PCI configuration header of > the PCI controller. > + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. > + > +**/ > +EFI_STATUS > +ProgramMaxReadReqSize ( > + IN PCI_IO_DEVICE *PciDevice, > + IN VOID *PciExFeatureConfiguration > + ) > +{ > + PCI_REG_PCIE_DEVICE_CONTROL PcieDev; > + UINT32 Offset; > + EFI_STATUS Status; > + EFI_TPL OldTpl; > + > + PcieDev.Uint16 = 0; > + Offset = PciDevice->PciExpressCapabilityOffset + > + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); > + Status = PciDevice->PciIo.Pci.Read ( > + &PciDevice->PciIo, > + EfiPciIoWidthUint16, > + Offset, > + 1, > + &PcieDev.Uint16 > + ); > + ASSERT (Status == EFI_SUCCESS); > + > + if (PcieDev.Bits.MaxReadRequestSize != PciDevice->SetupMRRS) { > + PcieDev.Bits.MaxReadRequestSize = PciDevice->SetupMRRS; > + DEBUG (( DEBUG_INFO, "MRRS: %d,", PciDevice->SetupMRRS)); > + > + // > + // Raise TPL to high level to disable timer interrupt while the write > operation > completes > + // > + OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL); > + > + Status = PciDevice->PciIo.Pci.Write ( > + &PciDevice->PciIo, > + EfiPciIoWidthUint16, > + Offset, > + 1, > + &PcieDev.Uint16 > + ); > + // > + // Restore TPL to its original level > + // > + gBS->RestoreTPL (OldTpl); > + > + if (!EFI_ERROR(Status)) { > + PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 = > PcieDev.Uint16; > + } else { > + ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, > PciDevice->FunctionNumber, Offset); > + } > + } else { > + DEBUG (( DEBUG_INFO, "No MRRS=%d,", PciDevice->SetupMRRS)); } > + > + return Status; > +} > + > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h > index 460437b..b43fba7 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h > @@ -52,4 +52,49 @@ ProgramMaxPayloadSize ( > IN VOID *PciExFeatureConfiguration > ); > > + > +EFI_STATUS > +ConditionalCasMaxReadReqSize ( > + IN PCI_IO_DEVICE *PciDevice, > + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE > +*PciFeaturesConfigurationTable > + ); > + > +/** > + The main routine which process the PCI feature Max_Read_Req_Size as > +per the > + device-specific platform policy, as well as in complaince with the > +PCI Base > + specification Revision 4, that aligns the value for the entire PCI > +heirarchy > + starting from its physical PCI Root port / Bridge device. > + > + @param PciDevice A pointer to the PCI_IO_DEVICE. > + @param PciConfigPhase for the PCI feature configuration > phases: > + PciExpressFeatureSetupPhase & > + PciExpressFeatureEntendedSetupPhase > + @param PciFeaturesConfigurationTable pointer to > + PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE > + > + @retval EFI_SUCCESS processing of PCI feature > Max_Read_Req_Size > + is successful. > +**/ > +EFI_STATUS > +SetupMaxReadReqSize ( > + IN PCI_IO_DEVICE *PciDevice, > + IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE > +*PciFeaturesConfigurationTable > + ); > + > +/** > + Overrides the PCI Device Control register Max_Read_Req_Size register > +field; if > + the hardware value is different than the intended value. > + > + @param PciDevice A pointer to the PCI_IO_DEVICE instance. > + > + @retval EFI_SUCCESS The data was read from or written to the PCI > controller. > + @retval EFI_UNSUPPORTED The address range specified by Offset, Width, > and Count is not > + valid for the PCI configuration header of > the PCI controller. > + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. > + > +**/ > +EFI_STATUS > +ProgramMaxReadReqSize ( > + IN PCI_IO_DEVICE *PciDevice, > + IN VOID *PciExFeatureConfiguration > + ); > + > #endif > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > index aae6139..1caf1f4 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > @@ -34,7 +34,7 @@ EFI_PCI_EXPRESS_PLATFORM_POLICY > mPciExpressPlatformPolicy = { > // > // support for PCI Express feature - Max. Read Request Size > // > - FALSE, > + TRUE, > // > // support for PCI Express feature - Extended Tag > // > @@ -104,6 +104,15 @@ PCI_EXPRESS_FEATURE_INITIALIZATION_POINT > mPciExpressFeatureInitializationList[] > }, > { > PciExpressFeatureProgramPhase, PciExpressMps, > ProgramMaxPayloadSize > + }, > + { > + PciExpressFeatureSetupPhase, PciExpressMrrs, > SetupMaxReadReqSize > + }, > + { > + PciExpressFeatureEntendedSetupPhase, PciExpressMrrs, > ConditionalCasMaxReadReqSize > + }, > + { > + PciExpressFeatureProgramPhase, PciExpressMrrs, > ProgramMaxReadReqSize > } > }; > > @@ -607,6 +616,15 @@ CreatePciRootBridgeDeviceNode ( > // start by assuming 4096B as the default value for the Max. Payload Size > // > PciConfigTable->Max_Payload_Size = > PCIE_MAX_PAYLOAD_SIZE_4096B; > + // > + // start by assuming 4096B as the default value for the Max. Read Request > Size > + // > + PciConfigTable->Max_Read_Request_Size = > PCIE_MAX_READ_REQ_SIZE_4096B; > + // > + // start by assuming the Max. Read Request Size need not be common for > all > + // the devices in the PCI tree > + // > + PciConfigTable->Lock_Max_Read_Request_Size = FALSE; > } > > RootBridgeNode->PciExFeaturesConfigurationTable = PciConfigTable; diff -- > git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > index 4ecbefc..a1fc39c 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > @@ -71,6 +71,15 @@ struct > _PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE { > // size among all the PCI devices in the PCI hierarchy > // > UINT8 Max_Payload_Size; > + // > + // to configure the PCI feature maximum read request size to maintain > + the memory // requester size among all the PCI devices in the PCI > + hierarchy // > + UINT8 Max_Read_Request_Size; > + // > + // lock the Max_Read_Request_Size for the entire PCI tree of a root > + port // > + BOOLEAN Lock_Max_Read_Request_Size; > }; > > // > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > index 3e9d4c5..f74e566 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > @@ -115,6 +115,40 @@ SetDevicePolicyPciExpressMps ( > } > } > > +/** > + Routine to translate the given device-specific platform policy from > +type > + EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE to HW-specific value, as per PCI > +Base Specification > + Revision 4.0; for the PCI feature Max_Read_Req_Size. > + > + @param MRRS Input device-specific policy should be in terms of type > + EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE > + > + @retval Range values for the Max_Read_Req_Size as defined in the > PCI > + Base Specification 4.0 **/ > +UINT8 > +SetDevicePolicyPciExpressMrrs ( > + IN UINT8 MRRS > +) > +{ > + switch (MRRS) { > + case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_128B: > + return PCIE_MAX_READ_REQ_SIZE_128B; > + case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_256B: > + return PCIE_MAX_READ_REQ_SIZE_256B; > + case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_512B: > + return PCIE_MAX_READ_REQ_SIZE_512B; > + case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_1024B: > + return PCIE_MAX_READ_REQ_SIZE_1024B; > + case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_2048B: > + return PCIE_MAX_READ_REQ_SIZE_2048B; > + case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_4096B: > + return PCIE_MAX_READ_REQ_SIZE_4096B; > + default: > + return PCIE_MAX_READ_REQ_SIZE_128B; > + } > +} > + > /** > Generic routine to setup the PCI features as per its predetermined > defaults. > **/ > @@ -130,6 +164,12 @@ SetupDefaultPciExpressDevicePolicy ( > PciDevice->SetupMPS = EFI_PCI_EXPRESS_NOT_APPLICABLE; > } > > + if (mPciExpressPlatformPolicy.Mrrs) { > + PciDevice->SetupMRRS = EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_AUTO; > + } else { > + PciDevice->SetupMRRS = EFI_PCI_EXPRESS_NOT_APPLICABLE; } > + > } > > /** > @@ -211,6 +251,14 @@ GetPciExpressDevicePolicy ( > PciDevice->SetupMPS = EFI_PCI_EXPRESS_NOT_APPLICABLE; > } > > + // > + // set device specific policy for Max_Read_Req_Size > + // > + if (mPciExpressPlatformPolicy.Mrrs) { > + PciDevice->SetupMRRS = PciExpressDevicePolicy.DeviceCtlMRRS; > + } else { > + PciDevice->SetupMRRS = EFI_PCI_EXPRESS_NOT_APPLICABLE; > + } > > DEBUG (( > DEBUG_INFO, > @@ -327,6 +375,28 @@ GetPciExpressMps ( > return EFI_PCI_EXPRESS_NOT_APPLICABLE; } > > +EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE > +GetPciExpressMrrs ( > + IN UINT8 Mrrs > + ) > +{ > + switch (Mrrs) { > + case PCIE_MAX_READ_REQ_SIZE_128B: > + return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_128B; > + case PCIE_MAX_READ_REQ_SIZE_256B: > + return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_256B; > + case PCIE_MAX_READ_REQ_SIZE_512B: > + return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_512B; > + case PCIE_MAX_READ_REQ_SIZE_1024B: > + return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_1024B; > + case PCIE_MAX_READ_REQ_SIZE_2048B: > + return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_2048B; > + case PCIE_MAX_READ_REQ_SIZE_4096B: > + return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_4096B; > + } > + return EFI_PCI_EXPRESS_NOT_APPLICABLE; } > + > > /** > Notifies the platform about the current PCI Express state of the device. > @@ -358,6 +428,17 @@ PciExpressPlatformNotifyDeviceState ( > PciExDeviceConfiguration.DeviceCtlMPS = > EFI_PCI_EXPRESS_NOT_APPLICABLE; > } > > + // > + // get the device-specific state for the PCIe Max_Read_Req_Size > + feature // if (mPciExpressPlatformPolicy.Mrrs) { > + PciExDeviceConfiguration.DeviceCtlMRRS = GetPciExpressMrrs ( > + (UINT8)PciDevice- > >PciExpressCapabilityStructure.DeviceControl.Bits.MaxReadRequestSize > + ); } else { > + PciExDeviceConfiguration.DeviceCtlMRRS = > + EFI_PCI_EXPRESS_NOT_APPLICABLE; } > + > if (mPciExPlatformProtocol != NULL) { > return mPciExPlatformProtocol->NotifyDeviceState ( > mPciExPlatformProtocol, diff --git > a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > index 5ae6386..4653c79 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > @@ -101,4 +101,19 @@ SetDevicePolicyPciExpressMps ( > IN UINT8 MPS > ); > > +/** > + Routine to translate the given device-specific platform policy from > +type > + EFI_PCI_CONF_MAX_READ_REQ_SIZE to HW-specific value, as per PCI Base > +Specification > + Revision 4.0; for the PCI feature Max_Read_Req_Size. > + > + @param MRRS Input device-specific policy should be in terms of type > + EFI_PCI_CONF_MAX_READ_REQ_SIZE > + > + @retval Range values for the Max_Read_Req_Size as defined in the > PCI > + Base Specification 4.0 **/ > +UINT8 > +SetDevicePolicyPciExpressMrrs ( > + IN UINT8 MRRS > +); > #endif > -- > 2.21.0.windows.1 > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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