REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2698
To enhance FSP silicon initialization flexibility an optional Multi-Phase API is introduced and FSP header needs update for new API offset. Cc: Maurice Ma <[email protected]> Cc: Nate DeSimone <[email protected]> Cc: Star Zeng <[email protected]> Signed-off-by: Chasel Chiu <[email protected]> --- IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h index 16f43a1273..3474bac1de 100644 --- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h +++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h @@ -1,8 +1,8 @@ /** @file Intel FSP Header File definition from Intel Firmware Support Package External - Architecture Specification v2.0. + Architecture Specification v2.0 and above. - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -110,6 +110,12 @@ typedef struct { /// Byte 0x44: The offset for the API to initialize the CPU and chipset. /// UINT32 FspSiliconInitEntryOffset; + /// + /// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization. + /// This value is only valid if FSP HeaderRevision is >= 5. + /// If the value is set to 0x00000000, then this API is not available in this component. + /// + UINT32 FspMultiPhaseSiInitEntryOffset; } FSP_INFO_HEADER; /// -- 2.13.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#58351): https://edk2.groups.io/g/devel/message/58351 Mute This Topic: https://groups.io/mt/73367408/21656 Group Owner: [email protected] Unsubscribe: https://edk2.groups.io/g/devel/unsub [[email protected]] -=-=-=-=-=-=-=-=-=-=-=-
