From: Wasim Khan <wasim.k...@nxp.com> PCIe layerscape controller supports CFG Shift feature. It can be enabled by setting BIT[28] of iATU Control 2 Register. Check PcdPciCfgShiftEnable to enable 'CFG Shift feature' in PCIe controller. if enable, PCIe layerscape controller shifts BDF from bits[27:12] to bits[31:16] and supports Enhanced Configuration Address Mapping (ECAM) mechanism.
PCIe layerscape controller is ECAM complaint for bus[0x1-0xff]. So create outbound CFG windows from 1MB-256MB (255 buses) for type0/type1 configuration access. PCIe layerscape controller is Non-ECAM complaint for bus 0.It does not support device > 0 on bus 0. PciSegmentLib should handles this limitation. Signed-off-by: Vabhav Sharma <vabhav.sha...@nxp.com> Signed-off-by: Wasim Khan <wasim.k...@nxp.com> --- Silicon/NXP/NxpQoriqLs.dec | 3 ++ .../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 3 ++ Silicon/NXP/Include/Pcie.h | 3 ++ .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 35 +++++++++++++++++----- 4 files changed, 36 insertions(+), 8 deletions(-) diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index bafdfd9f4298..293fd773fd3d 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -36,3 +36,6 @@ [PcdsFixedAtBuild.common] gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x00000502 gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT32|0x00000503 gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE|BOOLEAN|0x00000504 + +[PcdsDynamic.common] + gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x00000600 diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf index 5ddb96e4fa6a..98cfb6aee6b0 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -38,3 +38,6 @@ [FixedPcd] gNxpQoriqLsTokenSpaceGuid.PcdNumPciController gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg + +[Pcd] + gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable diff --git a/Silicon/NXP/Include/Pcie.h b/Silicon/NXP/Include/Pcie.h index d5b5a3884e0a..ae85190180e8 100755 --- a/Silicon/NXP/Include/Pcie.h +++ b/Silicon/NXP/Include/Pcie.h @@ -63,6 +63,7 @@ #define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C #define IATU_VIEWPORT_OUTBOUND 0x0 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31 +#define IATU_ENABLE_CFG_SHIFT_FEATURE BIT28 // ATU Programming #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0 @@ -82,4 +83,6 @@ #define SEG_IO_SIZE 0x10000 #define SEG_IO_BUS 0x0 +#define CFG_SHIFT_ENABLE (PcdGetBool (PcdPciCfgShiftEnable)) + #endif diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c index cf872370c7cd..f92863c60868 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -259,8 +259,17 @@ PcieOutboundSet ( MmioWrite32 (Dbi + IATU_REGION_CTRL_1_OFF_OUTBOUND_0, (UINT32)Type); - MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0, - IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN); + if (CFG_SHIFT_ENABLE && + ((Type == IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0) || + (Type == IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1))) { + MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0, + (IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN | + IATU_ENABLE_CFG_SHIFT_FEATURE) + ); + } else { + MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN); + } } /** @@ -291,12 +300,22 @@ PcieLsSetupAtu ( UINT64 Cfg0Size; UINT64 Cfg1Size; - Cfg0BaseAddr = Cfg0Base; - Cfg1BaseAddr = Cfg1Base; - Cfg0BusAddress = SEG_CFG_BUS; - Cfg1BusAddress = SEG_CFG_BUS; - Cfg0Size = SEG_CFG_SIZE; - Cfg1Size = SEG_CFG_SIZE; + if (CFG_SHIFT_ENABLE) { + DEBUG ((DEBUG_INFO, "PCIe: CFG Shit Method Enabled \n")); + Cfg0BaseAddr = Cfg0Base + SIZE_1MB; + Cfg1BaseAddr = Cfg0Base + SIZE_2MB; + Cfg0BusAddress = SIZE_1MB; + Cfg1BusAddress = SIZE_2MB; + Cfg0Size = SIZE_1MB; + Cfg1Size = (SIZE_256MB - SIZE_1MB); // 255MB + } else { + Cfg0BaseAddr = Cfg0Base; + Cfg1BaseAddr = Cfg1Base; + Cfg0BusAddress = SEG_CFG_BUS; + Cfg1BusAddress = SEG_CFG_BUS; + Cfg0Size = SEG_CFG_SIZE; + Cfg1Size = SEG_CFG_SIZE; + } // iATU : OUTBOUND WINDOW 1 : CFG0 PcieOutboundSet (Pcie, -- 2.7.4 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#60122): https://edk2.groups.io/g/devel/message/60122 Mute This Topic: https://groups.io/mt/74396466/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-