From: Pankaj Bansal <pankaj.ban...@nxp.com>
Chassis3V2 is the new chassis on which LS1028A and LX2160A SOCs
are based.
Add the Chassis3V2 package.
Signed-off-by: Pankaj Bansal <pankaj.ban...@nxp.com>
Reviewed-by: Leif Lindholm <l...@nuviainc.com>
---
Notes:
V3:
- No change
V2:
- No change
Silicon/NXP/Chassis3V2/Chassis3V2.dec | 22 ++++++
Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc | 10 +++
Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf | 33 +++++++++
Silicon/NXP/Chassis3V2/Include/Chassis.h | 26 +++++++
Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c | 71
++++++++++++++++++++
5 files changed, 162 insertions(+)
diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dec
b/Silicon/NXP/Chassis3V2/Chassis3V2.dec
new file mode 100644
index 000000000000..f7269e6bf6de
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dec
@@ -0,0 +1,22 @@
+# @file
+# NXP Layerscape processor package.
+#
+# Copyright 2017, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 1.27
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
new file mode 100644
index 000000000000..b9f388a59f2a
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
@@ -0,0 +1,10 @@
+# @file
+#
+# Copyright 2018-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+ ChassisLib|Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
new file mode 100644
index 000000000000..75b68cc4ca2d
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
@@ -0,0 +1,33 @@
+# @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ INF_VERSION = 1.27
+ BASE_NAME = Chassis3V2Lib
+ FILE_GUID = fae0d077-5fc2-494f-b8e1-c51a3023ee3e
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ChassisLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/Chassis3V2/Chassis3V2.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ IoAccessLib
+ IoLib
+ PcdLib
+ SerialPortLib
+
+[Sources.common]
+ ChassisLib.c
+
+[FeaturePcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
diff --git a/Silicon/NXP/Chassis3V2/Include/Chassis.h
b/Silicon/NXP/Chassis3V2/Include/Chassis.h
new file mode 100644
index 000000000000..0fd70132d897
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Include/Chassis.h
@@ -0,0 +1,26 @@
+/** @file
+
+ Copyright 2018-2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef CHASSIS_H__
+#define CHASSIS_H__
+
+#include <Uefi.h>
+
+#define NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS 0x1E00000
+
+/**
+ The Device Configuration Unit provides general purpose configuration and
+ status for the device. These registers only support 32-bit accesses.
+**/
+#pragma pack(1)
+typedef struct {
+ UINT8 Reserved0[0x100 - 0x0];
+ UINT32 RcwSr[32]; // Reset Control Word Status Register
+} NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG;
+#pragma pack()
+
+#endif // CHASSIS_H__
diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
new file mode 100644
index 000000000000..30f8f945b233
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
@@ -0,0 +1,71 @@
+/** @file
+ Chassis specific functions common to all SOCs based on a specific Chessis
+
+ Copyright 2018-2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Chassis.h>
+#include <Uefi.h>
+#include <Library/IoAccessLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+
+/**
+ Read Dcfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+DcfgRead32 (
+ IN UINTN Address
+ )
+{
+ MMIO_OPERATIONS *DcfgOps;
+
+ DcfgOps = GetMmioOperations (FeaturePcdGet (PcdDcfgBigEndian));
+
+ return DcfgOps->Read32 (Address);
+}
+
+/**
+ Write Dcfg register
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+**/
+UINT32
+EFIAPI
+DcfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ MMIO_OPERATIONS *DcfgOps;
+
+ DcfgOps = GetMmioOperations (FeaturePcdGet (PcdDcfgBigEndian));
+
+ return DcfgOps->Write32 (Address, Value);
+}
+
+/**
+ Function to initialize Chassis Specific functions
+ **/
+VOID
+ChassisInit (
+ VOID
+ )
+{
+ //
+ // Early init serial Port to get board information.
+ //
+ SerialPortInitialize ();
+}
--
2.17.1
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