> On Jun 3, 2020, at 5:37 PM, Michael D Kinney <michael.d.kin...@intel.com>
> wrote:
>
> Hi Andrew,
>
> Are you referring to the order the fields are filled in by the C code
> before the x86 instruction is executed? I do not think that matters.
>
Mike,
The instructions point to a blob of data that is not UINTN aligned. These
register point to a limit then base address. If you execute the instruction you
get 2 bytes of limit and 4 or 8 bytes of data. But Idtr[0] is base and Intro[1]
is limit, so reversed from the instruction order. What defines index 0 vs.
index 1 data contents?
Thanks,
Andrew Fish
> Thanks,
>
> Mike
>
>> -----Original Message-----
>> From: devel@edk2.groups.io <devel@edk2.groups.io> On
>> Behalf Of Andrew Fish via groups.io
>> Sent: Wednesday, June 3, 2020 4:39 PM
>> To: edk2-devel-groups-io <devel@edk2.groups.io>
>> Subject: [edk2-devel] Does anyone know the definition of
>> EFI_SYSTEM_CONTEXT_X64.Gdtr[2] and
>> EFI_SYSTEM_CONTEXT_X64.Idtr[2]
>>
>> The x86 instructions do limit then base, but the code is
>> storing base, then limit. Does anyone remember if this
>> is properly defined some place?
>>
>> Thanks,
>>
>> Andrew Fish
>>
>
>
>
>
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