REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following files: * Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib * Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib Cc: Sai Chaganty <rangasai.v.chaga...@intel.com> Cc: Nate DeSimone <nathaniel.l.desim...@intel.com> Signed-off-by: Heng Luo <heng....@intel.com> --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf | 36 ++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.c | 18 ++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.inf | 39 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 174 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c new file mode 100644 index 0000000000..6a9bc89ecf --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c @@ -0,0 +1,81 @@ +/** @file + CPU PCIe information library. + + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#include <Uefi/UefiBaseType.h> +#include <Library/DebugLib.h> +#include <Library/BaseLib.h> +#include <Library/PciSegmentLib.h> +#include <Register/CpuPcieRegs.h> +#include <Library/CpuPcieInfoFruLib.h> +#include <Library/CpuPcieInitCommon.h> +#include <CpuPcieInfo.h> +#include <Register/SaRegsHostBridge.h> +#include <PcieRegs.h> + +/** + Get Maximum CPU Pcie Root Port Number + + @retval Maximum CPU Pcie Root Port Number +**/ +UINT8 +GetMaxCpuPciePortNum ( + VOID + ) +{ + return CPU_PCIE_ULT_ULX_MAX_ROOT_PORT; +} + +/** + Get CPU Pcie Root Port Device and Function Number by Root Port physical Number + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device number. + @param[out] RpFun Return corresponding root port function number. + + @retval EFI_SUCCESS Root port device and function is retrieved + @retval EFI_INVALID_PARAMETER RpNumber is invalid +**/ +EFI_STATUS +EFIAPI +GetCpuPcieRpDevFun ( + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFun + ) +{ + if (RpNumber > GetMaxCpuPciePortNum ()) { + DEBUG ((DEBUG_ERROR, "GetCpuPcieRpDevFun invalid RpNumber %x", RpNumber)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + // + // For TGL - U/Y only one CPU PCIE Root port is present + // + *RpDev = 6; + *RpFun = 0; + return EFI_SUCCESS; +} +/** + + Gets pci segment base address of PCIe root port. + + @param RpIndex Root Port Index (0 based) + + @return PCIe port base address. +**/ +UINT64 +CpuPcieBase ( + IN UINT32 RpIndex + ) +{ + UINTN RpDevice; + UINTN RpFunction; + GetCpuPcieRpDevFun (RpIndex, &RpDevice, &RpFunction); + return PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, (UINT32) RpDevice, (UINT32) RpFunction, 0); +} diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf new file mode 100644 index 0000000000..b6a40b2f7c --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf @@ -0,0 +1,36 @@ +## @file +# CPU PCIe information library for TigerLake PCH. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +[Defines] +INF_VERSION = 0x00010017 +BASE_NAME = PeiDxeSmmCpuPcieInfoFruLib +FILE_GUID = 59CA5352-ED46-4449-BF1C-0D0074C4D5B1 +VERSION_STRING = 1.0 +MODULE_TYPE = BASE +LIBRARY_CLASS = CpuPcieInfoFruLib + + +[LibraryClasses] +IoLib +BaseLib +DebugLib +PrintLib +PcdLib +ConfigBlockLib +CpuPcieInitCommonLib + +[Packages] +MdePkg/MdePkg.dec +TigerlakeSiliconPkg/SiPkg.dec + +[Sources] +CpuPcieInfoFruLib.c diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.c b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.c new file mode 100644 index 0000000000..d6e8096da6 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.c @@ -0,0 +1,18 @@ +/** @file + DXE FRU Library to initialize Vtd + + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#include <Base.h> + +/** + For device that specified by Device Num and Function Num, + mDevEnMap is used to check device presence. + 0x80 means use Device ID to detemine presence + 0x8F means force to update + + The structure is used to check if device scope is valid when update DMAR table +**/ +UINT16 mDevEnMap[][2] = {{0x0200, 0x80}, {0x0500, 0x80}, {0x1400, 0x80}, {0x1401, 0x80}, {0x0700, 0x80}, {0x0701, 0x80}, {0x0702, 0x80}, {0x0703, 0x80}, {0x1302, 0x8F}, {0x1303, 0x8F}}; +UINTN mDevEnMapSize = sizeof (mDevEnMap) / (sizeof (UINT16) * 2); diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.inf new file mode 100644 index 0000000000..e0aa88f68a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.inf @@ -0,0 +1,39 @@ +## @file +# Library description file for DXE Phase Vtd Init +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +[Defines] +INF_VERSION = 0x00010017 +BASE_NAME = DxeVtdInitFruLib +FILE_GUID = 18690D67-08A9-4DCE-B62D-CBE3AF7CFEE7 +VERSION_STRING = 1.0 +MODULE_TYPE = DXE_DRIVER +LIBRARY_CLASS = DxeVtdFruLib + + +[LibraryClasses] +UefiLib +UefiRuntimeServicesTableLib +UefiBootServicesTableLib +DebugLib +DxeSaPolicyLib + +[Packages] +MdePkg/MdePkg.dec +TigerlakeSiliconPkg/SiPkg.dec + +[Protocols] +gSaNvsAreaProtocolGuid ## CONSUMES + +[Sources] +DxeVtdInitFruLib.c + +[FixedPcd] + +[Guids] +gTcssHobGuid ## CONSUMES -- 2.24.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#71338): https://edk2.groups.io/g/devel/message/71338 Mute This Topic: https://groups.io/mt/80401173/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-