I have picked up the patches this morning and they are working as expected. Thanks, Leif.
Thanks Ashish ________________________________ From: Leif Lindholm <l...@nuviainc.com> Sent: Thursday, February 25, 2021 1:07 PM To: Ashish Singhal <ashishsin...@nvidia.com> Cc: ardb+tianoc...@kernel.org <ardb+tianoc...@kernel.org>; devel@edk2.groups.io <devel@edk2.groups.io> Subject: Re: [PATCH] ArmPkg/ArmGicLib: Fix setting GICv3 Interrupt Priority External email: Use caution opening links or attachments Hi Ashish, This bug was already reported by Ming (who also submitted a patch). Tracked in https://bugzilla.tianocore.org/show_bug.cgi?id=3236, should make it into the tree tomorrow. Thank you for your contribution! / Leif On Thu, Feb 25, 2021 at 10:19:46 -0700, Ashish Singhal wrote: > Incorrect register is being set for configuring interrupt > priority. Correct register is located in SGI space and not > in RD space. > > Signed-off-by: Ashish Singhal <ashishsin...@nvidia.com> > --- > ArmPkg/Drivers/ArmGic/ArmGicLib.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c > b/ArmPkg/Drivers/ArmGic/ArmGicLib.c > index 8ef32b3..3c0bee6 100644 > --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c > +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c > @@ -236,7 +236,7 @@ ArmGicSetInterruptPriority ( > } > > MmioAndThenOr32 ( > - GicCpuRedistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset), > + GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + > (4 * RegOffset), > ~(0xff << RegShift), > Priority << RegShift > ); > -- > 2.7.4 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#72286): https://edk2.groups.io/g/devel/message/72286 Mute This Topic: https://groups.io/mt/80907153/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
