From: Michael Kubacki <michael.kuba...@microsoft.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307

Updates PCDs to use the IntelSiliconPkg PCD tokenspace now that the
PCDs are declared in IntelSiliconPkg.dec.

Cc: Chasel Chiu <chasel.c...@intel.com>
Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
Signed-off-by: Michael Kubacki <michael.kuba...@microsoft.com>
---
 Platform/Intel/WhiskeylakeOpenBoardPkg/BiosInfo/BiosInfo.inf                   
                     |  4 +--
 Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf  
                     |  4 +--
 
Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapInclude.fdf 
                    |  4 +--
 
Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
 |  2 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf               
                     | 36 ++++++++++----------
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/FlashMapInclude.fdf
              |  4 +--
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf        
                     | 36 ++++++++++----------
 7 files changed, 45 insertions(+), 45 deletions(-)

diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/BiosInfo/BiosInfo.inf 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/BiosInfo/BiosInfo.inf
index a9687d93dee1..0a807ad84f4d 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/BiosInfo/BiosInfo.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/BiosInfo/BiosInfo.inf
@@ -36,8 +36,8 @@ [Packages]
   MinPlatformPkg/MinPlatformPkg.dec
 
 [Pcd]
-  gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase                    ## CONSUMES
-  gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize                    ## CONSUMES
+  gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase                    ## 
CONSUMES
+  gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize                    ## 
CONSUMES
 
 [Sources]
   BiosInfo.c
diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf
index 3233375d6568..537d507ed7d6 100644
--- 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf
+++ 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf
@@ -47,8 +47,8 @@ [Packages]
 
 [Pcd]
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress                     ## 
CONSUMES
-  gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase                          ## 
CONSUMES
-  gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize                          ## 
CONSUMES
+  gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase                ## 
CONSUMES
+  gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize                ## 
CONSUMES
   gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable
   gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformFlavor
   gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType
diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapInclude.fdf
 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapInclude.fdf
index f7aa730ae7d2..5895eebc5a79 100644
--- 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapInclude.fdf
+++ 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapInclude.fdf
@@ -38,8 +38,8 @@
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize          = 
0x00170000  #
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset              = 
0x00490000  # Flash addr (0xFFDE0000)
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize                = 
0x00070000  #
-SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset                  = 
0x00500000  # Flash addr (0xFFE50000)
-SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize                    = 
0x00050000  #
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset        = 
0x00500000  # Flash addr (0xFFE50000)
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize          = 
0x00050000  #
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset              = 
0x00550000  # Flash addr (0xFFEA0000)
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize                = 
0x000EA000  #
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset              = 
0x0063A000  # Flash addr (0xFFF8A000)
diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
index 2903bdacaebd..091d2118c7b3 100644
--- 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
+++ 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
@@ -293,7 +293,7 @@ [Pcd]
   gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
   gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
   gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
-  gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+  gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
 
 [FixedPcd]
   gSiPkgTokenSpaceGuid.PcdMchBaseAddress              ## CONSUMES
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
index 22fbfc99f0f0..8aea5aa475a0 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
@@ -31,8 +31,8 @@ [FD.UpXtreme]
 # assigned with PCD values. Instead, it uses the definitions for its variety, 
which
 # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.
 #
-BaseAddress   = $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress  
#The base address of the FLASH Device.
-Size          = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize             
#The size in bytes of the FLASH Device
+BaseAddress   = $(FLASH_BASE) | 
gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress  #The base address of the 
FLASH Device.
+Size          = $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize     
        #The size in bytes of the FLASH Device
 ErasePolarity = 1
 BlockSize     = $(FLASH_BLOCK_SIZE)
 NumBlocks     = $(FLASH_NUM_BLOCKS)
@@ -43,21 +43,21 @@ [FD.UpXtreme]
 # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro 
expression is not supported.
 # So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase to get 
the real CodeCache base address.
 SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = 
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
-SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = 
$(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + 
$(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
-SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 
$(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
-SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = 
$(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
-SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = 
$(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = 
$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + 
$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 
$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = 
$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = 
$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
 SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv     = 0x60
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase    = 
gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize    = 
gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset  = 
gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = 
gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize    = 
gSiPkgTokenSpaceGuid.PcdBiosSize
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress       = 
$(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + 
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress       = 
$(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + 
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress       = 
$(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + 
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress    = 
gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize           = 
gSiPkgTokenSpaceGuid.PcdBiosSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase    = 
gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize    = 
gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset  = 
gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = 
gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize    = 
gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress       = 
$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + 
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress       = 
$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + 
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress       = 
$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + 
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress    = 
gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize           = 
gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
 
################################################################################
 #
 # Following are lists of FD Region layout which correspond to the locations of 
different
@@ -158,8 +158,8 @@ [FD.UpXtreme]
 # FSP_S Section
 FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd
 
-gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
-gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
 #Microcode
 FV = FvMicrocode
 
diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/FlashMapInclude.fdf
 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/FlashMapInclude.fdf
index e0db38194211..586e3488c2a7 100644
--- 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/FlashMapInclude.fdf
+++ 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/FlashMapInclude.fdf
@@ -34,8 +34,8 @@
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize            = 
0x00190000  #
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset        = 
0x00320000  # Flash addr (0xFFB20000)
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize          = 
0x00170000  #
-SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset                  = 
0x00490000  # Flash addr (0xFFC90000)
-SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize                    = 
0x000B0000  #
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset        = 
0x00490000  # Flash addr (0xFFC90000)
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize          = 
0x000B0000  #
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset              = 
0x00540000  # Flash addr (0xFFD40000)
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize                = 
0x00070000  #
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset              = 
0x005B0000  # Flash addr (0xFFDB0000)
diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf
index 1ab8c137924e..f0601984338c 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf
@@ -31,8 +31,8 @@ [FD.WhiskeylakeURvp]
 # assigned with PCD values. Instead, it uses the definitions for its variety, 
which
 # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.
 #
-BaseAddress   = $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress    
  #The base address of the FLASH Device.
-Size          = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize             
#The size in bytes of the FLASH Device
+BaseAddress   = $(FLASH_BASE) | 
gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress  #The base address of the 
FLASH Device.
+Size          = $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize     
        #The size in bytes of the FLASH Device
 ErasePolarity = 1
 BlockSize     = $(FLASH_BLOCK_SIZE)
 NumBlocks     = $(FLASH_NUM_BLOCKS)
@@ -43,21 +43,21 @@ [FD.WhiskeylakeURvp]
 # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro 
expression is not supported.
 # So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase to get 
the real CodeCache base address.
 SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = 
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
-SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = 
$(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + 
$(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
-SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 
$(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
-SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = 
$(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
-SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = 
$(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = 
$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + 
$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 
$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = 
$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = 
$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
 SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv     = 0x60
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase    = 
gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize    = 
gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset  = 
gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = 
gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize    = 
gSiPkgTokenSpaceGuid.PcdBiosSize
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress       = 
$(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + 
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress       = 
$(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + 
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress       = 
$(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + 
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress    = 
gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize           = 
gSiPkgTokenSpaceGuid.PcdBiosSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase    = 
gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize    = 
gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset  = 
gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = 
gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize    = 
gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress       = 
$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + 
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress       = 
$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + 
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress       = 
$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + 
$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress    = 
gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize           = 
gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
 
################################################################################
 #
 # Following are lists of FD Region layout which correspond to the locations of 
different
@@ -153,8 +153,8 @@ [FD.WhiskeylakeURvp]
 
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
 FV = FvPostMemory
 
-gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
-gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
 #Microcode
 FV = FvMicrocode
 
-- 
2.28.0.windows.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#75321): https://edk2.groups.io/g/devel/message/75321
Mute This Topic: https://groups.io/mt/82929224/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-


Reply via email to