On Fri, Sep 24, 2021 at 05:38:21AM -0500, Brijesh Singh wrote:
> 
> On 9/24/21 5:11 AM, Yao, Jiewen wrote:
> > You are right. My statement for page table is wrong. Both TDX and SEV need 
> > them.
> >
> > That is NOT our original design. But I can understand why it is changed 
> > today.
> >
> > I compare 
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Ftianocore%2Fedk2-staging%2Fblob%2FTDVF%2FOvmfPkg%2FResetVector%2FX64%2FTdxMetadata.asm&data=04%7C01%7Cbrijesh.singh%40amd.com%7Cc5ee156422614a843cf408d97f43bc9b%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637680751169724127%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=GI6%2BzLASgUtBT9kS%2B%2BVDfzLlImYhZJeETpNfDMIimAk%3D&reserved=0
> >  and 
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2FAMDESE%2Fovmf%2Fblob%2Fsnp-v8%2FOvmfPkg%2FResetVector%2FX64%2FOvmfMetadata.asm&data=04%7C01%7Cbrijesh.singh%40amd.com%7Cc5ee156422614a843cf408d97f43bc9b%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637680751169724127%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Dq2pLkdBsYXFbYM5nmy43yv4DWn7IDUceMpQg2%2F0jYo%3D&reserved=0.
> >
> > There are 8 entries in TDX, and 10 entries in SEV.
> > 2 of them are same, page table and TEMP RAM.
> > 6 entries are TDX unique. 8 entries are SEV unique.
> 
> In the SEV patches you are seeing more sections because I tried to keep
> it in sync with the MEMFD [1] so that its much more readable.

We could add just a single range for stack + heap + pagetables  (+more?)
and comments saying which MEMFD areas are covered by that range, to keep
the table small.

take care,
  Gerd



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