Hi Leif, I assume you mean the commit description, because the commit message is in the topic. I believe something like that would do:
CpuExceptionHandlerLib supplies misaligned GDT to the outer world (e.g. ArchSetupExceptionStack) when PcdCpuStackGuard is enabled. This happens because it uses an array of UINT8 for the mNewGdt variable, which alignment is 1 byte versus required 8 bytes. As a result ArchSetupExceptionStack always returns EFI_INVALID_PARAMETER in OVMF Ia32 with XCODE5 and CLANGPDB at least. Fix this by allocating extra space in mNewGdt and then aligning the pointer upwards. Best wishes, Vitaly > On 5 Nov 2021, at 22:28, Leif Lindholm <l...@nuviainc.com> wrote: > > UefiCpuPkg maintainers - please respond. > > Meanwhile, Vitaly, could you please provide a commit message? > The BZ link is needed, but it's not a substitute. > > / > Leif > > On Mon, Sep 20, 2021 at 17:13:47 +0300, Vitaly Cheptsov wrote: >> REF: https://bugzilla.tianocore.org/show_bug.cgi?id639 >> >> >> >> Cc: Jiewen Yao <jiewen....@intel.com> >> >> Cc: Eric Dong <eric.d...@intel.com> >> >> Cc: Michael Kinney <michael.d.kin...@intel.com> >> >> Cc: Jian J Wang <jian.j.w...@intel.com> >> >> Cc: Jeff Fan <vanjeff_...@hotmail.com> >> >> Cc: Mikhail Krichanov <kricha...@ispras.ru> >> >> Cc: Marvin Häuser <mhaeu...@posteo.de> >> >> Signed-off-by: Vitaly Cheptsov <chept...@ispras.ru> >> >> --- >> >> .../Library/CpuExceptionHandlerLib/DxeException.c | 12 +++++++----- >> >> 1 file changed, 7 insertions(+), 5 deletions(-) >> >> >> >> diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c >> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c >> >> index fd59f09ecd..12874811e1 100644 >> >> --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c >> >> +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c >> >> @@ -22,7 +22,7 @@ EXCEPTION_HANDLER_DATA mExceptionHandlerData; >> >> >> >> UINT8 mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER * >> >> CPU_KNOWN_GOOD_STACK_SIZE]; >> >> -UINT8 mNewGdt[CPU_TSS_GDT_SIZE]; >> >> +UINT8 mNewGdt[CPU_TSS_GDT_SIZE + IA32_GDT_ALIGNMENT]; >> >> >> >> /** >> >> Common exception handler. >> >> @@ -238,6 +238,7 @@ InitializeCpuExceptionHandlersEx ( >> >> CPU_EXCEPTION_INIT_DATA EssData; >> >> IA32_DESCRIPTOR Idtr; >> >> IA32_DESCRIPTOR Gdtr; >> >> + UINT8 *Gdt; >> >> >> >> // >> >> // To avoid repeat initialization of default handlers, the caller should >> pass >> >> @@ -259,6 +260,7 @@ InitializeCpuExceptionHandlersEx ( >> >> if (PcdGetBool (PcdCpuStackGuard)) { >> >> if (InitData == NULL) { >> >> SetMem (mNewGdt, sizeof (mNewGdt), 0); >> >> + Gdt = ALIGN_POINTER (mNewGdt, IA32_GDT_ALIGNMENT); >> >> >> >> AsmReadIdtr (&Idtr); >> >> AsmReadGdtr (&Gdtr); >> >> @@ -270,11 +272,11 @@ InitializeCpuExceptionHandlersEx ( >> >> EssData.X64.StackSwitchExceptionNumber = >> CPU_STACK_SWITCH_EXCEPTION_NUMBER; >> >> EssData.X64.IdtTable = (VOID *)Idtr.Base; >> >> EssData.X64.IdtTableSize = Idtr.Limit + 1; >> >> - EssData.X64.GdtTable = mNewGdt; >> >> - EssData.X64.GdtTableSize = sizeof (mNewGdt); >> >> - EssData.X64.ExceptionTssDesc = mNewGdt + Gdtr.Limit + 1; >> >> + EssData.X64.GdtTable = Gdt; >> >> + EssData.X64.GdtTableSize = CPU_TSS_GDT_SIZE; >> >> + EssData.X64.ExceptionTssDesc = Gdt + Gdtr.Limit + 1; >> >> EssData.X64.ExceptionTssDescSize = CPU_TSS_DESC_SIZE; >> >> - EssData.X64.ExceptionTss = mNewGdt + Gdtr.Limit + 1 + >> CPU_TSS_DESC_SIZE; >> >> + EssData.X64.ExceptionTss = Gdt + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE; >> >> EssData.X64.ExceptionTssSize = CPU_TSS_SIZE; >> >> >> >> InitData = &EssData; >> >> -- >> >> 2.30.1 (Apple Git-130) >> >> >> >> >> >> >> >> -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#83406): https://edk2.groups.io/g/devel/message/83406 Mute This Topic: https://groups.io/mt/85741694/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
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