Changes in V2: - Moved FSP dispatch mode PCD additions for GalagoPro3 to a seperate patch series
This patch series sets the DUTY_OFFSET and DUTY_WIDTH fields in the ACPI FADT to 1 and 3 respectively. This will enable OS power management to set the CPU clock speed in the P_CNT register on these platforms. Cc: Chasel Chiu <chasel.c...@intel.com> Cc: Ankit Sinha <ankit.si...@intel.com> Cc: Sai Chaganty <rangasai.v.chaga...@intel.com> Cc: Michael Kubacki <michael.kuba...@microsoft.com> Cc: Heng Luo <heng....@intel.com> Cc: Deepika Kethi Reddy <deepika.kethi.re...@intel.com> Cc: Kathappan Esakkithevar <kathappan.esakkithe...@intel.com> Cc: Benjamin Doron <benjamin.doro...@gmail.com> Cc: Jeremy Soller <jer...@system76.com> Signed-off-by: Nate DeSimone <nathaniel.l.desim...@intel.com> Nate DeSimone (4): KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT .../CometlakeURvp/OpenBoardPkgPcd.dsc | 9 ++++++++- .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 9 ++++++++- .../GalagoPro3/OpenBoardPkgPcd.dsc | 8 +++++++- .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 11 +++++++++-- .../TigerlakeURvp/OpenBoardPkgPcd.dsc | 10 +++++++++- .../UpXtreme/OpenBoardPkgPcd.dsc | 9 ++++++++- .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 9 ++++++++- 7 files changed, 57 insertions(+), 8 deletions(-) -- 2.27.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90266): https://edk2.groups.io/g/devel/message/90266 Mute This Topic: https://groups.io/mt/91589971/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
