The patch replaces
LinearAddress + Offset == RegionStart
with
((LinearAddress + Offset) & RegionMask) == 0
The replace should not cause any behavior change.
Because:
1. In first loop of while when LinearAddress + Offset == RegionStart,
because the lower "BitStart" bits of RegionStart are all-zero,
all lower "BitStart" bits of (LinearAddress + Offset) are all-zero.
Because all lower "BitStart" bits of RegionMask is all-one and
bits are all-zero, ((LinearAddress + Offset) & RegionMask) == 0.
2. In following loops of the while, even RegionStart is increased
by RegionLength, the lower "BitStart" bits are still all-zero.
So the two expressions still semantically equal to each other.
Signed-off-by: Ray Ni <ray...@intel.com>
Cc: Zhiguang Liu <zhiguang....@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
---
UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index 429b014b7b..509fa5f7bd 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -360,7 +360,7 @@ PageTableLibMapInLevel (
PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS
(&ParentPagingEntry->Pnle);
while (Offset < Length && Index < 512) {
SubLength = MIN (Length - Offset, RegionStart + RegionLength -
(LinearAddress + Offset));
- if ((Level <= MaxLeafLevel) && (LinearAddress + Offset == RegionStart) &&
(SubLength == RegionLength)) {
+ if ((Level <= MaxLeafLevel) && (((LinearAddress + Offset) & RegionMask) ==
0) && (SubLength == RegionLength)) {
//
// Create one entry mapping the entire region (1G, 2M or 4K).
//
--
2.35.1.windows.2
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