The default SMBASE for the x86 processor is 0x30000. When
SMI happens, CPU runs the SMI handler at SMBASE+0x8000.
Also, the SMM save state area is within SMBASE+0x10000.
One of the SMM initialization from CPU perspective is to
program the new SMBASE (in TSEG range) for each CPU thread.
When the SMBASE relocated happens in one PEI module ahead
of the PiSmmCpuDxeSmm, the PEI module shall produce the
SMM_BASE_HOB in HOB database which tells the PiSmmCpuDxeSmm
driver which runs at a later phase about the new SMBASE for
each CPU thread. PiSmmCpuDxeSmm driver shall install the
SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for
CPU thread Index. When the HOB doesn't exist,
PiSmmCpuDxeSmm driver shall program the new SMBASE itself.
This patch adds the SMM Base HOB, which can be produced
by any PEI module to do the SmBase relocation ahead of
PiSmmCpuDxeSmm driver and store the relocated SmBase
address in array for reach Processors.
Cc: Eric Dong <eric.d...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Zeng Star <star.z...@intel.com>
Cc: Laszlo Ersek <ler...@redhat.com>
Cc: Gerd Hoffmann <kra...@redhat.com>
Cc: Rahul Kumar <rahul1.ku...@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin...@intel.com>
---
UefiCpuPkg/Include/Guid/SmmBaseHob.h | 49 ++++++++++++++++++++++++++++++++++++
UefiCpuPkg/UefiCpuPkg.dec | 3 +++
2 files changed, 52 insertions(+)
create mode 100644 UefiCpuPkg/Include/Guid/SmmBaseHob.h
diff --git a/UefiCpuPkg/Include/Guid/SmmBaseHob.h
b/UefiCpuPkg/Include/Guid/SmmBaseHob.h
new file mode 100644
index 0000000000..6ed32481dc
--- /dev/null
+++ b/UefiCpuPkg/Include/Guid/SmmBaseHob.h
@@ -0,0 +1,49 @@
+/** @file
+ The Smm Base HOB is used to store the information of:
+ * The relocated SmBase in array for each Processors.
+
+ The default SMBASE for the x86 processor is 0x30000. When SMI happens,
+ CPU runs the SMI handler at SMBASE+0x8000. Also, the SMM save state
+ area is within SMBASE+0x10000.
+
+ One of the SMM initialization from CPU perspective is to program the
+ new SMBASE (in TSEG range) for each CPU thread. When the SMBASE update
+ happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB
+ in HOB database which tells the PiSmmCpuDxeSmm driver which runs at a
+ later phase about the new SMBASE for each CPU thread. PiSmmCpuDxeSmm
+ driver installs the SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000
+ for CPU thread Index. When the HOB doesn't exist, PiSmmCpuDxeSmm driver
+ shall program the new SMBASE itself.
+
+ Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SMM_BASE_HOB_H_
+#define SMM_BASE_HOB_H_
+
+#include <Protocol/MpService.h>
+#include <PiPei.h>
+
+#define SMM_BASE_HOB_DATA_GUID \
+ { \
+ 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d,
0x73} \
+ }
+
+#pragma pack(1)
+typedef struct {
+ ///
+ /// Describes the Number of all max supported processors.
+ ///
+ UINT64 NumberOfProcessors;
+ ///
+ /// Pointer to SmBase address for each Processors.
+ ///
+ UINT64 SmBase[];
+} SMM_BASE_HOB_DATA;
+#pragma pack()
+
+extern EFI_GUID gSmmBaseHobGuid;
+
+#endif
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index cff239d528..2afd08cdd2 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -76,10 +76,13 @@
gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e,
0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}
## Include/Guid/MicrocodePatchHob.h
gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31,
0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}
+ ## Include/Guid/SmmBaseHob.h
+ gSmmBaseHobGuid = { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c,
0x25, 0xc5, 0xfc, 0x9d, 0x73 }}
+
[Protocols]
## Include/Protocol/SmmCpuService.h
gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94,
0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}
gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9,
0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }}
--
2.16.2.windows.1
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