Thanks Ray, I will update all you mentioned.
> -----Original Message----- > From: Ni, Ray <ray...@intel.com> > Sent: Thursday, February 16, 2023 12:59 PM > To: Wu, Jiaxin <jiaxin...@intel.com>; devel@edk2.groups.io > Cc: Dong, Eric <eric.d...@intel.com>; Zeng, Star <star.z...@intel.com>; > Laszlo Ersek <ler...@redhat.com>; Gerd Hoffmann <kra...@redhat.com>; > Kumar, Rahul R <rahul.r.ku...@intel.com> > Subject: RE: [PATCH v8 3/6] UefiCpuPkg/SmmBaseHob.h: Add SMM Base HOB > Data > > > > > -----Original Message----- > > From: Wu, Jiaxin <jiaxin...@intel.com> > > Sent: Thursday, February 16, 2023 10:47 AM > > To: devel@edk2.groups.io > > Cc: Dong, Eric <eric.d...@intel.com>; Ni, Ray <ray...@intel.com>; Zeng, Star > > <star.z...@intel.com>; Laszlo Ersek <ler...@redhat.com>; Gerd Hoffmann > > <kra...@redhat.com>; Kumar, Rahul R <rahul.r.ku...@intel.com> > > Subject: [PATCH v8 3/6] UefiCpuPkg/SmmBaseHob.h: Add SMM Base HOB > > Data > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337 > > > > The default SMBASE for the x86 processor is 0x30000. When > > SMI happens, CPU runs the SMI handler at SMBASE+0x8000. > > Also, the SMM save state area is within SMBASE+0x10000. > > > > One of the SMM initialization from CPU perspective is to relocate > > and program the new SMBASE (in TSEG range) for each CPU thread. When > > the SMBASE relocation happens in a PEI module, the PEI module shall > > produce the SMM_BASE_HOB in HOB database which tells the > > PiSmmCpuDxeSmm driver (runs at a later phase) about the new SMBASE > > for each CPU thread. PiSmmCpuDxeSmm driver installs the SMI handler > > at the SMM_BASE_HOB.SmBase[Index]+0x8000 for CPU thread Index. When > > the HOB doesn't exist, PiSmmCpuDxeSmm driver shall relocate and > > program the new SMBASE itself. > > > > This patch adds the SMM Base HOB for any PEI module to do > > the SmBase relocation ahead of PiSmmCpuDxeSmm driver and > > store the relocated SmBase address in array for reach > > Processors. > > > > Cc: Eric Dong <eric.d...@intel.com> > > Cc: Ray Ni <ray...@intel.com> > > Cc: Zeng Star <star.z...@intel.com> > > Cc: Laszlo Ersek <ler...@redhat.com> > > Cc: Gerd Hoffmann <kra...@redhat.com> > > Cc: Rahul Kumar <rahul1.ku...@intel.com> > > Signed-off-by: Jiaxin Wu <jiaxin...@intel.com> > > --- > > UefiCpuPkg/Include/Guid/SmmBaseHob.h | 75 > > ++++++++++++++++++++++++++++++++++++ > > UefiCpuPkg/UefiCpuPkg.dec | 5 ++- > > 2 files changed, 79 insertions(+), 1 deletion(-) > > create mode 100644 UefiCpuPkg/Include/Guid/SmmBaseHob.h > > > > diff --git a/UefiCpuPkg/Include/Guid/SmmBaseHob.h > > b/UefiCpuPkg/Include/Guid/SmmBaseHob.h > > new file mode 100644 > > index 0000000000..9434276991 > > --- /dev/null > > +++ b/UefiCpuPkg/Include/Guid/SmmBaseHob.h > > @@ -0,0 +1,75 @@ > > +/** @file > > + The Smm Base HOB is used to store the information of: > > + * The relocated SmBase address in array for each Processors. > > 1. Processors -> processor. > > > + CPU runs the SMI handler at Smbase+0x8000. Also, the SMM save state > area is > > 2. better align the term to use processor. > MP protocol also uses the term "processor" > > > + > > + Note: > > + 1. Smbase relocation process needs to program the vender specific > > hardware > > + interface to set Smbase, it should be in the thread scope. It's doable to > > 3. "it should be in the thread scope" -> "it might be in the thread scope". > The HOB itself doesn't have "thread scope" requirement. > With the "thread scope" possibility, following statement looks good to me. > Just change "should be" to "might be". > > > +#pragma pack(1) > > +typedef struct { > > + /// > > + /// CpuIndex tells which CPU range this specific HOB instance described. > > + /// If CpuIndex is set to 0, it indicats the HOB describes the CPU from > > 0 to > > + /// NumberOfCpus - 1. The HOB list may contains multiple this HOB > > instances. > > + /// Each HOB instances describe the information for CPU from CpuIndex to > > + /// CpuIndex + NumberOfCpus - 1. The instance order in the HOB list is > > random > > + /// so consumer can not assume the CpuIndex of first instance is 0. > > + /// > > + UINT32 CpuIndex; > > 4. "ProcessorIndex". Please also update the comments to use "processor". -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100271): https://edk2.groups.io/g/devel/message/100271 Mute This Topic: https://groups.io/mt/96998933/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
